Abstract: An iron-doped high-electron-mobility transistor (HEMT) structure includes a substrate, a nucleation layer over the substrate, and a buffer layer over the nucleation layer. The gallium-nitride buffer layer includes a iron-doping-stop layer having a concentration of iron that drops from a juncture with an iron-doped component of the buffer layer over a thickness that is relatively small compared to that of the iron-doped component. The iron-doping-stop layer is formed at lower temperature compared to the temperature at which the iron-doped component is formed. The iron-doped HEMT structure also includes a channel layer over the buffer layer. A carrier-supplying barrier layer is formed over the channel layer.

Abstract: An iron-doped high-electron-mobility transistor (HEMT) structure includes a substrate, a nucleation layer over the substrate, and a buffer layer over the nucleation layer. The gallium-nitride buffer layer includes a iron-doping-stop layer having a concentration of iron that drops from a juncture with an iron-doped component of the buffer layer over a thickness that is relatively small compared to that of the iron-doped component. The iron-doping-stop layer is formed at lower temperature compared to the temperature at which the iron-doped component is formed. The iron-doped HEMT structure also includes a channel layer over the buffer layer. A carrier-supplying barrier layer is formed over the channel layer.

Abstract: A semiconductor device includes an etch-stop layer between a first layer of a field-effect transistor and a second layer of a bipolar transistor, each of which includes at least one arsenic-based semiconductor layer. A p-type layer is between the second layer and the etch-stop layer, and the device can include an n-type layer deposited between the etch-stop layer and p-type layer. The p-type layer provides an electric field that inhibits intermixing of the InGaP layer with layers in the first and second layers.

Abstract: An epitaxial structure on a substrate includes a gallium nitride buffer layer over the substrate and a graded channel layer over the gallium nitride layer. The graded channel layer consists essentially of InxGa1-xN wherein the value of x gets smaller from a first surface of the channel layer proximate to a buffer layer to a second surface remote from the buffer layer.