Patents Assigned to Isemicon, Inc.
  • Publication number: 20080262771
    Abstract: A method of fault detection and classification in semiconductor manufacturing is provided. In the method, delicate variations of actual data of parameters for which normal values of a manufacturing condition change according to time are detected very precisely and sensitively, and accordingly major variation components for a step which has a high occurrence occupancy are acquired to achieve a very precise and effective fault detection and classification (FDC). In the method, continuous steps in a process are regarded as separate processes which are not related to each other and covariance and covariance inverse matrixes acquired for each step are set as references to decrease values of variance or covariance compared with those for a case where references are calculated based on total steps. Accordingly, Hotelling's T-square values for a small variation are increased, so that a delicate variation can be sensitively detected.
    Type: Application
    Filed: November 1, 2006
    Publication date: October 23, 2008
    Applicant: ISEMICON, INC.
    Inventors: Heung Seob Koo, Jae Keun Lee
  • Patent number: 6714885
    Abstract: A method for measuring the number of yield loss chips and the number of poor chips by type due to defects of semiconductor chips by which it is possible to remarkably improve the yield of semiconductor chips by measuring the number of yield loss chips due to defects of the chips, the maximum number of yield loss chips, and the number of the specific type of poor chips in an arbitrary process, an arbitrary equipment, and an arbitrary process section among semiconductor fabrication processes, thus managing the defects of the chips, is provided.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: March 30, 2004
    Assignee: Isemicon, Inc.
    Inventor: Jae-keun Lee