Patents Assigned to Isetex, Inc
  • Patent number: 6882022
    Abstract: A Dual Gate BCMD pixel has a compact size, nondestructive readout; complete reset with no kTC-reset noise generation, anti-blooming protection, and column reset capability. By incorporating a dual gate MOS transistor with an enclosed annular layout into the pixels of image sensing array, and sensing photo-generated charge nondestructively by detecting the transistor threshold voltage variations caused by collected charge, achieves this goal and other objects of the invention.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: April 19, 2005
    Assignee: Isetex, Inc
    Inventor: Jaroslav Hynecek
  • Patent number: 6680222
    Abstract: Generally, and in one form of the invention, a monolithic solid state image-sensing device is disclosed. The device utilizes only a single layer of polysilicon deposition in its fabrication process that is split into two or more phases by very narrow gaps. The single polysilicon layer makes the fabrication process simpler and more compatible with modern semiconductor manufacturing technology. The device also incorporates a lateral anti-blooming drain structure that is formed by a self-aligned diffusion process and does not need a polysilicon gate for its proper function.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: January 20, 2004
    Assignee: Isetex, Inc
    Inventor: Jaroslav Hynecek
  • Patent number: 6278142
    Abstract: A charge carrier multiplier is disclosed in which a carrier that passes through a high-field region lying entirely within the depleted semiconductor volume causes a single-step impact ionization without avalanching. By spacing the high-field region sufficiently away from any substrate region that is not depleted of carriers of opposite polarity than the ionizing carrier, generation of unwanted spurious charge is minimized. Preferably the cell includes a depleted channel formed in a substrate, a gate structure insulatively disposed over and transverse to the channel having an aperture formed therein, and a charge multiplication gate electrode insulatively disposed over the aperture. In one embodiment, the gate electrode structure includes a first aperture gate electrode having the aperture formed therethrough, and in another embodiment, the gate electrode structure includes first and second aperture gate electrodes having respective first and second reticulations therein so as to frame the aperture.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: August 21, 2001
    Assignee: Isetex, Inc
    Inventor: Jaroslav Hynecek