Abstract: A hardware circuit implemented on a DRAM foundry is provided for finding the longest prefix key match. The hardware circuit includes the use of prefix search engines to store prefix keys. Each prefix search engine may advantageously include an n-dimension memory for fast efficient access. Each prefix search engine is preassigned to store prefix keys having a specific length. Based on the preassignment and the n-dimensional memory, the hardware circuit matches the longest prefix key stored in the prefix search engines by comparing all prefix search engines in parallel.

Abstract: A hardware circuit implemented on a DRAM foundry is provided for finding the longest prefix key match. The hardware circuit includes the use of prefix search engines to store prefix keys. Each prefix search engine may advantageously include an n-dimension memory for fast efficient access. Each prefix search engine is preassigned to store prefix keys having a specific length. Based on the preassignment and the n-dimensional memory, the hardware circuit matches the longest prefix key stored in the prefix search engines by comparing all prefix search engines in parallel.

Abstract: A mechanism is provided for efficiently storing a key and optionally additional data in an environment. A memory apparatus embodiment includes a plurality of memory banks and a conversion module. The number of memory banks is determined by at least the number of coordinates within an n-dimension format, each bank is associated to one of the coordinates within the n-dimension format. Each memory bank has at least a number of memory locations equal to the largest valid value for its associated coordinate. The conversion module converts a key into an n-dimension format, the n-dimension format defines a coordinate system where each coordinate represents a memory location within the associated memory bank. The conversion module stores the key into one memory location based on a policy which is dependent on the coordinates defined by the n-dimension format.

Abstract: Techniques are provided for performing modular arithmetic on a key composed of many bits. One circuit implementation includes a distributor, one or more lookup tables and a plurality of adders. The distributor segments the key into a plurality of partitions. Each partition is based on a polynomial expression corresponding to a fixed size key. Each of the bits contained within the partitions are routed on a partition basis to one or more lookup tables, the routed bits acting as indices into the one or more tables. The lookup tables store precomputed values based upon the polynomial expression. The outputted precomputed values from one or more lookup tables are outputted to the plurality of adders. The plurality of adders add the bits from a portion of the routed partitions and the outputted precomputed values from the one or more lookup tables to form the binary residue.

Abstract: A hardware circuit implemented on a DRAM foundry is provided for finding the longest prefix key match. The hardware circuit includes the use of prefix search engines to store prefix keys. Each prefix search engine may advantageously include an n-dimension memory for fast efficient access. Each prefix search engine is preassigned to store prefix keys having a specific length. Based on the preassignment and the n-dimensional memory, the hardware circuit matches the longest prefix key stored in the prefix search engines by comparing all prefix search engines in parallel.

Abstract: Techniques are provided for performing modular arithmetic on a key composed of many bits. One circuit implementation includes a distributor, one or more lookup tables and a plurality of adders. The distributor segments the key into a plurality of partitions. Each partition is based on a polynomial expression corresponding to a fixed size key. Each of the bits contained within the partitions are routed on a partition basis to one or more lookup tables, the routed bits acting as indices into the one or more tables. The lookup tables store precomputed values based upon the polynomial expression. The outputted precomputed values from one or more lookup tables are outputted to the plurality of adders. The plurality of adders add the bits from a portion of the routed partitions and the outputted precomputed values from the one or more lookup tables to form the binary residue.

Abstract: A mechanism is provided for efficiently storing a key and optionally additional data in an environment. A memory apparatus embodiment includes a plurality of memory banks and a conversion module. The number of memory banks is determined by at least the number of coordinates within an n-dimension format, each bank is associated to one of the coordinates within the n-dimension format. Each memory bank has at least a number of memory locations equal to the largest valid value for its associated coordinate. The conversion module converts a key into an n-dimension format, the n-dimension format defines a coordinate system where each coordinate represents a memory location within the associated memory bank. The conversion module stores the key into one memory location based on a policy which is dependent on the coordinates defined by the n-dimension format.