Patents Assigned to Istor Networks, Inc.
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Publication number: 20100235465Abstract: Disclosed is a system and methods for acceleration of the TCP/IP and the iSCSI protocols. The methods may be adapted to a wide variety of systems and applications that employ communications protocols including TCP, with or without iSCSI. Using a hardware-based acceleration approach, common case network traffic is rapidly processed at near line rate thereby improving overall performance and alleviating processing bottlenecks.Type: ApplicationFiled: September 21, 2009Publication date: September 16, 2010Applicant: iStor Networks, Inc.Inventors: Roger Thorpe, Jeffrey Oliver Thomas, Itsik Yomorta, Ting-Kuo Yu, Erasmo Javier Brenes
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Publication number: 20090248830Abstract: A storage networking device provides remote direct memory access to its buffer memory, configured to store storage networking data. The storage networking device may be particularly adapted to transmit and receive iSCSI data, such as iSCSI input/output operations. The storage networking device comprises a controller and a buffer memory. The controller manages the receipt of storage networking data and buffer locational data. The storage networking data advantageously includes at least one command for at least partially controlling a device attached to a storage network. Advantageously, the storage networking data may be transmitted using a protocol adapted for the transmission of storage networking data, such as, for example, the iSCSI protocol. The buffer memory advantageously is configured to at least temporarily store at least part of the storage networking data at a location within the buffer memory that is based at least in part on the locational data.Type: ApplicationFiled: March 31, 2009Publication date: October 1, 2009Applicant: iSTOR NETWORKS, INC.Inventors: Jean Kodama, Michael Morrison
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Patent number: 7594002Abstract: Disclosed is a system and methods for acceleration of the TCP/IP and the iSCSI protocols. The methods may be adapted to a wide variety of systems and applications that employ communications protocols including TCP, with or without iSCSI. Using a hardware-based acceleration approach, common case network traffic is rapidly processed at near line rate thereby improving overall performance and alleviating processing bottlenecks.Type: GrantFiled: February 17, 2004Date of Patent: September 22, 2009Assignee: Istor Networks, Inc.Inventors: Roger Thorpe, Jeffrey Oliver Thomas, Itsik Yomorta, Ting-Kuo Yu, Erasmo Javier Brenes
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Patent number: 7512663Abstract: Mechanisms and processes for directly storing data into the memory of a storage device using the iSCSI protocol are described. One mechanism includes a transmitting device that encodes data to be stored in an iSCSI protocol data unit. Also encoded is buffer locational data that indicates, directly or indirectly, one or more memory addresses of where the data is to be stored within the buffer memory of a receiving device. The buffer locational data is encoded using standard fields within the iSCSI protocol data unit, such as the Target Transfer Tag. A receiving device decodes the buffer locational data and stores the received data at the memory locations specified by the buffer locational data.Type: GrantFiled: February 18, 2004Date of Patent: March 31, 2009Assignee: iStor Networks, Inc.Inventors: Jean Kodama, Michael Morrison
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Publication number: 20090073884Abstract: Disclosed is a system and methods for accelerating network packet processing for devices configured to process network traffic at relatively high data rates. The system incorporates a hardware-accelerated packet processing module that handles in-sequence network packets and a software-based processing module that handles out-of-sequence and exception case network packets.Type: ApplicationFiled: December 1, 2008Publication date: March 19, 2009Applicant: ISTOR NETWORKS, INC.Inventors: Jean Kodama, Li Xu
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Publication number: 20090063696Abstract: Disclosed is a system and methods for accelerating network protocol processing for devices configured to process network traffic at relatively high data rates. The system incorporates a hardware-accelerated protocol processing module that handles steady state network traffic and a software-based processing module that handles infrequent and exception cases in network traffic processing.Type: ApplicationFiled: June 16, 2008Publication date: March 5, 2009Applicant: iStor Networks, Inc.Inventors: Linghsiao Wang, Li Xu
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Patent number: 7460473Abstract: Disclosed is a system and methods for accelerating network packet processing for devices configured to process network traffic at relatively high data rates. The system incorporates a hardware-accelerated packet processing module that handles in-sequence network packets and a software-based processing module that handles out-of-sequence and exception case network packets.Type: GrantFiled: February 17, 2004Date of Patent: December 2, 2008Assignee: Istor Networks, Inc.Inventors: Jean Kodama, Li Xu
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Patent number: 7389462Abstract: Disclosed is a system and methods for accelerating network protocol processing for devices configured to process network traffic at relatively high data rates. The system incorporates a hardware-accelerated protocol processing module that handles steady state network traffic and a software-based processing module that handles infrequent and exception cases in network traffic processing.Type: GrantFiled: February 17, 2004Date of Patent: June 17, 2008Assignee: iStor Networks, Inc.Inventors: Linghsiao Wang, Li Xu
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Patent number: 7353306Abstract: A bi-directional reflective memory channel between a pair of storage controllers is used to maintain a mirrored copy of each storage controller's native buffer contents within the buffer of the other storage controller. To maintain such mirrored copies, buffer write operations that fall within a reflective memory segment of one storage controller are automatically reflected across this channel to the other storage controller for execution, and vice versa. The write operations are preferably transmitted across the reflective memory channel using a protocol that provides for error checking, acknowledgements, and retransmissions. This protocol is preferably implemented entirely in automated circuitry, so that the mirrored copies are maintained without any CPU intervention during error-free operation. When a failover occurs, the surviving storage controller uses the mirrored copy of the failed storage controller's native buffer contents to assume control over the failed storage controller's disk drives.Type: GrantFiled: April 29, 2005Date of Patent: April 1, 2008Assignee: iStor Networks, Inc.Inventors: Roger T. Thorpe, Erasmo Brenes, Stephen O'Neil, Alec Shen
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Publication number: 20070288792Abstract: A bi-directional reflective memory channel between a pair of storage controllers is used to maintain a mirrored copy of each storage controller's native buffer contents within the buffer of the other storage controller. To maintain such mirrored copies, buffer write operations that fall within a reflective memory segment of one storage controller are automatically reflected across this channel to the other storage controller for execution, and vice versa. The write operations are preferably transmitted across the reflective memory channel using a protocol that provides for error checking, acknowledgements, and retransmissions. This protocol is preferably implemented entirely in automated circuitry, so that the mirrored copies are maintained without any CPU intervention during error-free operation. When a failover occurs, the surviving storage controller uses the mirrored copy of the failed storage controller's native buffer contents to assume control over the failed storage controller's disk drives.Type: ApplicationFiled: August 8, 2007Publication date: December 13, 2007Applicant: ISTOR NETWORKS, INC.Inventors: Roger Thorpe, Erasmo Brenes, Stephen O'Neil, Alec Shen
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Patent number: 6941396Abstract: A bi-directional reflective memory channel between a pair of storage controllers is used to maintain a mirrored copy of each storage controller's native buffer contents within the buffer of the other storage controller. To maintain such mirrored copies, buffer write operations that fall within a reflective memory segment of one storage controller are automatically reflected across this channel to the other storage controller for execution, and vice versa. The write operations are preferably transmitted across the reflective memory channel using a protocol that provides for error checking, acknowledgements, and retransmissions. This protocol is preferably implemented entirely in automated circuitry, so that the mirrored copies are maintained without any CPU intervention during error-free operation. When a failover occurs, the surviving storage controller uses the mirrored copy of the failed storage controller's native buffer contents to assume control over the failed storage controller's disk drives.Type: GrantFiled: February 19, 2003Date of Patent: September 6, 2005Assignee: Istor Networks, Inc.Inventors: Roger T. Thorpe, Erasmo Brenes, Stephen O'Neil, Alec Shen