Abstract: Disclosed is a system and methods for acceleration of the TCP/IP and the iSCSI protocols. The methods may be adapted to a wide variety of systems and applications that employ communications protocols including TCP, with or without iSCSI. Using a hardware-based acceleration approach, common case network traffic is rapidly processed at near line rate thereby improving overall performance and alleviating processing bottlenecks.

Abstract: Disclosed is a system and methods for acceleration of the TCP/IP and the iSCSI protocols. The methods may be adapted to a wide variety of systems and applications that employ communications protocols including TCP, with or without iSCSI. Using a hardware-based acceleration approach, common case network traffic is rapidly processed at near line rate thereby improving overall performance and alleviating processing bottlenecks.

Abstract: Mechanisms and processes for directly storing data into the memory of a storage device using the iSCSI protocol are described. One mechanism includes a transmitting device that encodes data to be stored in an iSCSI protocol data unit. Also encoded is buffer locational data that indicates, directly or indirectly, one or more memory addresses of where the data is to be stored within the buffer memory of a receiving device. The buffer locational data is encoded using standard fields within the iSCSI protocol data unit, such as the Target Transfer Tag. A receiving device decodes the buffer locational data and stores the received data at the memory locations specified by the buffer locational data.

Abstract: Disclosed is a system and methods for accelerating network protocol processing for devices configured to process network traffic at relatively high data rates. The system incorporates a hardware-accelerated protocol processing module that handles steady state network traffic and a software-based processing module that handles infrequent and exception cases in network traffic processing.

Abstract: Disclosed is a system and methods for accelerating network packet processing for devices configured to process network traffic at relatively high data rates. The system incorporates a hardware-accelerated packet processing module that handles in-sequence network packets and a software-based processing module that handles out-of-sequence and exception case network packets.

Abstract: Disclosed is a system and methods for accelerating network protocol processing for devices configured to process network traffic at relatively high data rates. The system incorporates a hardware-accelerated protocol processing module that handles steady state network traffic and a software-based processing module that handles infrequent and exception cases in network traffic processing.

Abstract: A bi-directional reflective memory channel between a pair of storage controllers is used to maintain a mirrored copy of each storage controller's native buffer contents within the buffer of the other storage controller. To maintain such mirrored copies, buffer write operations that fall within a reflective memory segment of one storage controller are automatically reflected across this channel to the other storage controller for execution, and vice versa. The write operations are preferably transmitted across the reflective memory channel using a protocol that provides for error checking, acknowledgements, and retransmissions. This protocol is preferably implemented entirely in automated circuitry, so that the mirrored copies are maintained without any CPU intervention during error-free operation. When a failover occurs, the surviving storage controller uses the mirrored copy of the failed storage controller's native buffer contents to assume control over the failed storage controller's disk drives.

Abstract: A bi-directional reflective memory channel between a pair of storage controllers is used to maintain a mirrored copy of each storage controller's native buffer contents within the buffer of the other storage controller. To maintain such mirrored copies, buffer write operations that fall within a reflective memory segment of one storage controller are automatically reflected across this channel to the other storage controller for execution, and vice versa. The write operations are preferably transmitted across the reflective memory channel using a protocol that provides for error checking, acknowledgements, and retransmissions. This protocol is preferably implemented entirely in automated circuitry, so that the mirrored copies are maintained without any CPU intervention during error-free operation. When a failover occurs, the surviving storage controller uses the mirrored copy of the failed storage controller's native buffer contents to assume control over the failed storage controller's disk drives.