Patents Assigned to IT Technologies, Inc.
  • Publication number: 20100115272
    Abstract: Methods are provided for processing a packet received by a mesh-enabled access point (MAP). When a first MAP receives a packet it can determine whether the packet is destined for a mesh portal based on the destination address. If so, the first MAP can retrieve an encryption key corresponding to the mesh portal, use the encryption key to encrypt the packet and set a mesh forwarding flag in the packet to indicate that the packet is destined for a mesh portal, and is encrypted with an encryption key corresponding to the mesh portal, and then forward the packet to the next hop MAP towards the a mesh portal. The mesh forwarding flag indicates that the packet is destined for a mesh portal, is encrypted with an encryption key corresponding to the mesh portal, and is to be forwarded to the next hop MAP without performing decryption/re-encryption processing on the packet. When a MAP receives a packet, the first MAP it determines whether a mesh forwarding flag is set in the packet.
    Type: Application
    Filed: October 30, 2008
    Publication date: May 6, 2010
    Applicant: SYMBOL TECHNOLOGIES, INC.
    Inventor: Puneet BATTA
  • Publication number: 20100112294
    Abstract: A metallic foil tape having a top surface and a bottom surface with an adhesive applied to at least one of the top surface or the bottom surface of the metallic foil tape and corrugations in the metallic foil tape providing for expansion of the corrugated metallic foil tape in a circular or semi-circular shape. The corrugated metallic foil tape is suitable to be applied to contoured or three-dimensional surfaces, and is particularly suitable for use in sealing or joining components of heat, ventilation, and air conditioning (HVAC) units.
    Type: Application
    Filed: November 4, 2008
    Publication date: May 6, 2010
    Applicant: Shurtape Technologies, Inc.
    Inventor: Muzaffer Fidan
  • Publication number: 20100115116
    Abstract: Methods and systems are disclosed including those that cause an electronic interface device to dynamically switch protocols that it uses to communicate with a host to which the electronic interface device is connected. In one such embodiment, the electronic interface device first attempts using a first communications protocol, such as a CCID protocol. If the host contains a driver for the first communications protocol, the host communicates with the electronic interface device using the first communications protocol. If the host does not contain a driver for the first communications protocol, the electronic interface device attempts using a second communications protocol that is different from the first communications protocol, such as a HID protocol. The host then communicates with the electronic interface device using the second communications protocol.
    Type: Application
    Filed: November 3, 2008
    Publication date: May 6, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: MEHDI ASNAASHARI
  • Publication number: 20100109705
    Abstract: A device for shifting voltage levels includes an input stage, an output stage and multiple cascode sets connected between the input stage and the output stage. The input stage includes input transistors connected to a first voltage and an input for receiving an input signal. The output stage includes output transistors connected to a second voltage and an output for outputting an output signal having a voltage level different from a corresponding voltage level of the input signal. Each cascode set includes corresponding cascode transistors gated to a third voltage, which is between the first voltage and the second voltage, preventing excessive voltage across terminals of the input transistors and the output transistors.
    Type: Application
    Filed: November 3, 2008
    Publication date: May 6, 2010
    Applicant: AGILENT TECHNOLOGIES, INC.
    Inventor: Jill Marie PAMPERIN
  • Publication number: 20100115190
    Abstract: A system for processing a read request for maximizing host read performance in a flash memory-based storage device is provided. The system for processing the read request solves a bottleneck phenomenon caused by a processor by adding an independent automatic read request processor, different from a conventional system in which a processor of a storage device processes the read request. Also, when processing the read request, a storage device using a write buffer may control a process of merging data of the write buffer and a flash memory and transmitting the data to a host based on a descriptor array, thereby minimizing processor overhead.
    Type: Application
    Filed: January 24, 2008
    Publication date: May 6, 2010
    Applicants: Zeen Information Technologies, Inc., Seoul National University Industry Foundation
    Inventors: Yookun Cho, Sang Lyul Min, Jin Hyuk Yoon, Sung-Kwan Kim, Joosun Hahn
  • Publication number: 20100110898
    Abstract: An apparatus comprising a data framer configured to frame an external protocol extension message for transmission, the external protocol extension message comprising a header that indicates an external protocol extension and at least one type-length-value (TLV) comprising a type field, a length field, and a value field, wherein a format of the TLV is specified by a specific organization, and wherein the value field comprises information related to protocol functions external to the network. Also included is an apparatus comprising at least one component configured to implement a method comprising compiling an external protocol extension message comprising a plurality of TLVs and a header that indicates an external protocol extension, and transmitting the external protocol message.
    Type: Application
    Filed: August 21, 2009
    Publication date: May 6, 2010
    Applicant: Futurewei Technologies, Inc.
    Inventors: Frank J. Effenberger, Bo Gao, Wei Lin
  • Publication number: 20100115347
    Abstract: Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor. The pattern-recognition processor may include or be coupled to a results buffer, which may have a plurality of records, a write-control module configured to write data relevant to search results in the plurality of records, and a read control module configured to read data from the plurality of records.
    Type: Application
    Filed: November 5, 2008
    Publication date: May 6, 2010
    Applicant: Micron Technology, Inc.
    Inventor: Harold B Noyes
  • Publication number: 20100112710
    Abstract: The present invention relates to compositions and methods for detection and quantification of individual target molecules in biomolecular samples. In particular, the invention relates to coded, labeled probes that are capable of binding to and identifying target molecules based on the probes' label codes. Methods, computers, and computer program products for identifying target-specific sequences for inclusion in the probes are also provided, as are methods of making and using such probes. The probes can be used in diagnostic, prognostic, quality control and screening applications.
    Type: Application
    Filed: April 10, 2008
    Publication date: May 6, 2010
    Applicant: NANOSTRING TECHNOLOGIES, INC.
    Inventors: Gary K. Geiss, Tim Dahl, Craig E. Dahl, Eric H. Davidson
  • Publication number: 20100112778
    Abstract: A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.
    Type: Application
    Filed: January 13, 2010
    Publication date: May 6, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Gurtej S. Sandhu, D.V. Nirmal Ramaswamy
  • Publication number: 20100110083
    Abstract: Included are embodiments of systems and methods for processing metacommands. In at least one exemplary embodiment a Graphics Processing Unit (GPU) includes a metaprocessor configured to process at least one context register, the metaprocessor including context management logic and a metaprocessor control register block coupled to the metaprocessor, the metaprocessor control register block configured to receive metaprocessor configuration data, the metaprocessor control register block further configured to define metacommand execution logic block behavior. Some embodiments include a Bus Interface Unit (BIU) configured to provide the access from a system processor to the metaprocessor and a GPU command stream processor configured to fetch a current context command stream and send commands for execution to a GPU pipeline and metaprocessor.
    Type: Application
    Filed: November 6, 2008
    Publication date: May 6, 2010
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Timour Paltashev, Boris Prokopenko, John Brothers
  • Publication number: 20100110604
    Abstract: An electrostatic chuck and method for clamping a workpiece is provided. The ESC comprises a clamping plate having a clamping surface, and one or more electrodes. An electric potential applied to the one or more electrodes selectively clamps the workpiece to the clamping surface. A punch is operably coupled to the clamping plate and an electrical ground, wherein the punch comprises a trigger mechanism and a punch tip. The punch tip translates between extended and retracted positions, wherein a point of the punch tip is proud of the clamping surface when the punch tip is in the extended position. The punch tip is configured to translate toward the clamping surface upon clamping the workpiece to the clamping plate. Upon reaching the retracted position, the trigger mechanism imparts an impact force to the punch tip, forcing the punch tip into the workpiece and providing an electrical ground connection to the workpiece.
    Type: Application
    Filed: October 31, 2008
    Publication date: May 6, 2010
    Applicant: Axcelis Technologies, Inc.
    Inventors: David B. Smith, William D. Lee, Marvin R. LaFontaine, Ashwin M. Purohit
  • Publication number: 20100111782
    Abstract: The invention relates to a process for the production of alkylated aromatic compounds comprising introducing olefin and aromatic compounds into at least first and second vertically spaced catalytic reaction zones in an alkylation unit under alkylation reaction conditions to provide an alkylated product, wherein the second catalytic reaction zone is positioned above the first catalytic reaction zone; wherein aromatic compound from each of the at least first and second catalytic reaction zones are contacted with a cooling means for re-condensing at least a portion of the aromatic compounds vaporized from the exothermic heat of reaction of the alkylation process; and wherein the olefin is introduced into the at least first and second catalytic reaction zones via respective first and second olefin feed streams at respective olefin feed rates such as to maintain olefin partial pressures at inlets to at least first and second catalytic reaction zones which vary by less than about ten percent.
    Type: Application
    Filed: December 11, 2009
    Publication date: May 6, 2010
    Applicant: LUMMUS TECHNOLOGY INC.
    Inventor: Kevin J. SCHWINT
  • Publication number: 20100115244
    Abstract: A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline execution pipeline is configured for generating a thread context (TC) flush indicator associated with a thread context when one or more instructions of the thread context would stall in the execution pipeline. One or more instructions in the pipeline of the thread context associated with the thread context flush signal can be flushed or nullified.
    Type: Application
    Filed: January 8, 2010
    Publication date: May 6, 2010
    Applicant: MIPS Technologies, Inc.
    Inventors: Michael Gottlieb Jensen, Darren M. JONES, Ryan C. Kinter, Sanjay Vishin
  • Publication number: 20100115162
    Abstract: A redundant storage virtualization computer system is provided. The redundant storage virtualization computer system comprises a host entity for issuing an IO request, a redundant storage virtualization controller set coupled to the host entity for performing an IO operation in response to the IO request issued by the host entity, and a plurality of physical storage devices for providing storage space to the computer system. Each of the physical storage devices is coupled to the redundant storage virtualization controller set. The redundant storage virtualization controller set comprises a first and a second storage virtualization controller both coupled to the host entity, the storage virtualization controllers communicate therebetween via a PCI-Express interconnect.
    Type: Application
    Filed: January 7, 2010
    Publication date: May 6, 2010
    Applicant: INFORTREND TECHNOLOGY, INC.
    Inventors: Teh-Chern Chou, Wei-Shun Huang
  • Publication number: 20100115243
    Abstract: A fork instruction for execution on a multithreaded microprocessor and occupying a single instruction issue slot is disclosed. The fork instruction, executing in a parent thread, includes a first operand specifying the initial instruction address of a new thread and a second operand. The microprocessor executes the fork instruction by allocating context for the new thread, copying the first operand to a program counter of the new thread context, copying the second operand to a register of the new thread context, and scheduling the new thread for execution. If no new thread context is free for allocation, the microprocessor raises an exception to the fork instruction. The fork instruction is efficient because it does not copy the parent thread general purpose registers to the new thread. The second operand is typically used as a pointer to a data structure in memory containing initial general purpose register set values for the new thread.
    Type: Application
    Filed: October 23, 2009
    Publication date: May 6, 2010
    Applicant: MIPS Technologies, Inc.
    Inventor: Kevin D. KISSELL
  • Publication number: 20100114542
    Abstract: Included are methods for modeling at least one physical property of a mixture of at least two chemical species. One or more chemical species of the mixture are approximated or represented by at least one conceptual segment. The conceptual segments are then used to compute at least one physical property of the mixture. An analysis of the computed physical properties forms a model of at least one physical property of the mixture. Also included are computer program products and computer systems for implementing the modeling methods.
    Type: Application
    Filed: January 11, 2010
    Publication date: May 6, 2010
    Applicant: Aspen Technology, Inc.
    Inventors: Chau-Chyun Chen, Yuhua Song
  • Publication number: 20100109431
    Abstract: The invention is a device and method for eliminating core excitation losses in a distribution transformer when the transformer is not supplying power to loads. The invention consists of sensors, a control circuit, a user interface and a power contactor. The power contactor is connected on the line side of a transformer and is opened or closed automatically based on preprogrammed time or load criteria determined by the control circuit. In one operational mode and when the transformer is disconnected from the line, the control board generates low power pulses at the transformer load connection points in order to “search” for loads. If a load is detected, the transformer is reconnected by way of contactor closure. If the transformer load drops to zero, for a predetermined amount of time, the transformer is again disconnected and the pulsed load search is reestablished.
    Type: Application
    Filed: January 12, 2010
    Publication date: May 6, 2010
    Applicant: XANTREX TECHNOLOGY INC.
    Inventor: Rick West
  • Publication number: 20100111715
    Abstract: A pump system has a rotatory shaft and a rotatory drive arrangement coupled to the rotatory shaft for applying rotatory energy thereto. First through fourth pump arrangements are coupled to the rotatory shaft, each pump arrangement pumping a pulse of air during each rotation of the rotatory shaft, the first, second, third, and fourth pump arrangements pumping a corresponding pulse of air sequentially during each rotation of the rotatory shaft. The rotatory shaft has a first and second ends, and a central region therebetween where an electric motor is coaxially arranged. The first and third pump arrangements are coupled to the first end of the rotatory shaft, and the second and fourth pump arrangements are coupled to the second end of the rotatory shaft. Angularly displaced eccentric couplers couple the pump arrangements to the respective ends of the rotatory shaft.
    Type: Application
    Filed: August 17, 2007
    Publication date: May 6, 2010
    Applicant: L*VAD TECHNOLOGY, INC.
    Inventors: Paul G. DeDecker, Paul S. Freed
  • Publication number: 20100107609
    Abstract: A method for controlling a selective catalytic reduction catalyst in an exhaust line of an internal combustion engine is disclosed, wherein the supply of a quantity of a gaseous ammonia reductant to the SCR catalyst uses a closed-loop SCR catalyst model coupled to a SCR-out NOx sensor that measures a SCR-out NOx emission value. The closed-loop SCR catalyst model uses a relationship linking the measured SCR-out NOx value to the NOx conversion efficiency and the ammonia slip. The actual NH3 emission value and/or an actual SCR-out NOx indicative value are computed based upon differentiation of said relationship.
    Type: Application
    Filed: October 28, 2009
    Publication date: May 6, 2010
    Applicant: DELPHI TECHNOLOGIES, INC.
    Inventors: MICHAEL PARMENTIER, JULIEN SCHMITT
  • Publication number: 20100112467
    Abstract: Several embodiments of photolithography systems and associated methods of overlay error correction are disclosed herein. In one embodiment, a method for correcting overlay errors in a photolithography system includes measuring a plurality of first overlay errors that individually correspond to a microelectronic substrate in a first batch of microelectronic substrates. The method also includes determining a relationship between the first overlay errors and a first sequence of the microelectronic substrates in the first batch. The method further includes correcting a second overlay error of individual microelectronic substrates in a second batch based on a second sequence of the microelectronic substrates in the second batch and the determined relationship.
    Type: Application
    Filed: November 6, 2008
    Publication date: May 6, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Woong Jae Chung