Abstract: The provision of an intermediately doped transition region between respective n+ implanted source and drain regions in a GaAs FET and the lightly doped channel region under the gate permits device optimizaiton for low source and drain resistance in EFET's while employing the same n+ implant for source and drain optimization in DFET's while also maintaining the same n+ to gate contact spacing in both device types. Additionally, in high frequency operation of an asymmetrically implanted FET, the tapered doping profile offered by the transition region on the drain side of the gate provides high transconductance without sacrificing high output resistance. The transition region can be provided in a self-aligned implant employing dielectric sidewall spacers and the n+ implant can be self-aligned with an etch mask employed in gate definition.

Abstract: A photo-detector in the form of an optical field effect transistor comprig a semi-insulating InP substrate (1), a p.sup.+InP gate region ( 2) an n.sup.- InGaAs channel region (3) and source and drain contacts (5,6). Light incident on the bottom face of the substrate is detected. The channel region is thicker and reduced in doping in comparison with a normal JFET in order to achieve efficient light absorption and low gate to source capacitance. The source and drain contacts are interdigitated to increase the area for optical absorption (FIG. 1). Alternatively, (FIG. 2), the channel region is a composite structure including a lowly doped layer (11) for directing photogenerated carriers to a more highly doped layer (12) (active channel layer) of reduced dimensions of reduced area and upon which strip-like source and drain contacts (9,10) are disposed. The optical FET structures proposed facilitate integration with other circuit elements.

Abstract: A process for manufacturing gallium arsenide microwave circuits makes use of a nonphotosensitive acid resist as an adhesive for holding the "front side" of a gallium arsenide wafer onto a substrate while operations such as etching "via holes" into the wafer are being performed on the "back side" of the wafer. The process comprises front side processing, spinning the nonphotosensitive acid resist onto the frontside of the GaAs wafer, baking the protective acid resist coating onto the wafer, spinning the acid resist onto a substrate, joining the wafer to the substrate, thinning the wafer, and performing backside processing.

Abstract: A method and structure are disclosed for mounting and connecting an electic device such as an integrated circuit to a circuit board. The board has a plurality of embedded shielded conductors for interconnecting the integrated circuit to other devices on the board. In order to limit the capacitance and inductance of the connection, the integrated circuit is mass bonded directly to the conductors and to their coaxial shields.

Abstract: A photoconductor comprising an optically sensitive FET in which an abrupt heterojunction (18) is inserted in the channel (11) at a certain distance from the gate contact (16). This provides a potential barrier (17, FIG. 4) in the valence band that accumulates minority carriers (carriers of the lower mobility type) and controls their release. A gate bias resistor which is conventionally used in a receiver circuit including the FET is no longer required, instead the potential barrier height determines the time constant and a response comparable in length with an input optical pulse is achieved. This overcomes the problems of integrated manufacture, and slow response, associated with the large value of the bias resistor which is needed to reduce noise.

Abstract: A self-aligned gate structure for a compound semiconductor MESFET is formed rom a lower silicon layer and an upper metal, e.g. nickel, region. The nickel region forms an etch mask for the silicon and subsequently an implantation mask for the drain and source regions. Etching of the silicon provides an undercut whereby the gate separation from the drain and source is defined. Heating the structure to anneal the implant diffuses the metal into the silicon to form a compound silicide gate structure.

Abstract: A multifunction monolithic microwave integrated circuit composed of a pluity of dual gate FET amplifier sections connected between a pair of transmission lines which are adapted to receive one or two input signals. The circuit can be configured, by selective external connections and biasing voltage levels, to function in a number of different modes, such as an amplifier, a mixer, modulator, a variable amplifier, an attenuator, a temperature compensation chip, a frequency multiplier and a phase shifter.

Abstract: A method of making a field-effect transistor includes performing a first ion implant in at least one region of a gallium arsenide substrate and forming a metallization layer of titanium-tungsten nitride on the implanted substrate. A metallic gold masking layer is deposited on the metallization layer over the implanted region and that portion of the metallization layer which is unmasked is removed. A self-aligned source of implantation ions is beamed into the first implanted region in those areas not covered by the masking layer. The substrate is then annealed to activate the implanted region with the gold masking layer remaining to greatly reduce the resistance of the gate electrode of said field-effect transistor.

Abstract: Integrated circuits are tested prior to separation from a processed wafer. ach circuit has photoreceivers coupled via metallization tracks to an adjacent circuit. The receivers are used for the input of high speed optical test signals. The intercircuit coupling tracks are severed when the wafer is scribed to separate the individual circuits thus removing the electrical parasitic effects of the receivers.

Abstract: The gate of a gallium indium arsenide FET grown on an indium phosphide substrate comprises a top layer of GaInAsP (band gap 1.2 eV) a middle layer of GaInAs and a bottom layer of InP. This can be etched to produce an overhanging top layer which allows self-aligned gate contact metallization avoiding the registration problems of a further masking stage.

Abstract: A high frequency, e.g. millimeter wave, semiconductor diode structure includes a buried layer of n.sup.+ -type material and a surface layer of lightly doped n-type material on which a Schottky barrier contact is disposed. The n.sup.+ -type layer provides a low series resistance thus permitting high frequency operation. The structure is compatible with MESFET processing techniques and may thus be incorporated in an integrated circuit.

Abstract: A photo-detector includes a photoconductor comprised by a structure similar o a high electron mobility transistor (HEMT) but with the gate removed and the layer of high band gap thinned in order to reduce noise. On a semi-insulating substrate (8), an n-channel layer (9) is disposed and on channel layer (9) is disposed on n.sup.+ layer (7). Light incident on the n.sup.+ layer (7) causes electron-hole pairs to be generated in layer 9, the electrons and holes of which migrate to oppositely biased contact regions 10 and 11 respectively. The photoconductor is monolithically integrated with an HEMT (TI) (FIG. 3, FIG. 4 or FIG. 6) the latter comprising a pre-amplifier for a receiver circuit. In dependence on the materials chosen the photo-detector may be employed to detect wavelengths of the order of <8.88 .mu.m or <1.6 .mu.m.

Abstract: A jumper for interconnecting a plurality of wafer scale assemblies includes pair of grooves proximate the bending points thereof to relieve stresses introduced by bending forces.

Abstract: A semiconductor chip housing provides hermetic sealing and appropriate electrical characteristics for use at high frequencies. The housing comprises a substrate in which the chip is mounted and a cylindrical tube having a top cover and extending above the substrate which impinges on a base and thus hermetically seals the chip. Microthin leads extend from the substrate periphery to the chip. The leads carrying high frequency signals have notches therein to compensate for the impedance introduced by the tube and to enable the microstrip to present a constant impedance at high frequencies throughout its length.

Abstract: A gallium arsenide isolator has a common gate FET for amplifying a microw signal, the common gate FET being connected to a common drain FET for transmitting the microwave signal and for isolating the common gate FET from signals travelling in a direction opposite to the microwave signal. One or more L-C networks are connected at one end between the input and output of the isolator and at the other end to ground. The circulator includes three arms each having a gallium arsenide isolator. Each of the arms is coupled to another one of the arms by means of a four port coupler which permits transmission of a signal from one port to a second diagonally opposite port, the third port receiving a fixed fraction of the power and the fourth port receiving effectively no power.