Abstract: The proposed technique provides simultaneous read and writes from a display controller using low-cost SDRAMs. This is achieved, in one example embodiment, by receiving a sequence of video frames at a first variable frame rate. A first video frame is then written in a first single-ported memory. The first video frame is then read from the first single-ported memory upon completing the writing of the first video frame in the first single-ported memory. The reading of the first video frame is then repeated from the first single-ported memory to maintain a second frame rate. The second frame rate is higher than the first variable frame rate. A second video frame is then written in a second single-ported memory upon completing the writing of the first video frame in the first single-ported memory such that the writing of the first video frame and the second video frame is at the first variable frame rate.

Abstract: A method and apparatus for a frequency shift keying (FSK) demodulator use a configuration to improve the autocorrelation for better receiver performance. The demodulator uses parallel first and second lines connected to the same input signal, the first line having a delay element to provide an integer-delay of M, the second parallel line having a filter for causing a group delay of ?+M where ? is fractional, and a multiplier for receiving the signals from said first and second lines and generating a resultant signal from which a base band signal can be recovered. The resultant signal is passed through a low pass base band filter to recover the base band signal. ? may have a value of 3.25 and M may be 6. The demodulator may selectively be implemented in caller ID service and in low end modems chosen from a group comprising V.21, Bell 103, V.23 and Bell 202A modems.

Abstract: A decision feedback equalizer (DFE) has an inter symbol interference (ISI) loop and inter chip interference (ICI) loop. A buffer at the input of the DFE loop receives a (CCK based data rate) signal coming into the DFE, retains a predetermined number of chips from each incoming symbol and assists to meet timing requirements by chip management. An outgoing rate for the chips from the buffer may depend on the incoming rate and may be higher than the incoming rate by a known factor. A method of designing a configuration for the DFE takes into consideration the timing delay in the loops. The operation within the DFE loop is pipelined, and any latency due to the pipelining is handled at a CCK demodulator. A method for designing the DFE architecture and an article comprising a storage medium with instructions thereon for executing the method, are also disclosed.

Abstract: A method for designing a decision feedback equalizer (DFE) that handles packet based input data signals uses an inter symbol interference (ISI) removal loop and an inter chip interference (ICI) removal loop which is nested inside the ISI loop, for maximum interference removal and limited error propagation. The DFE may use a feed forward filter and a series connected chip-flow control buffer for receiving the input data signals. The DFE of the invention has application in 802.11 b PHY and 802.11 g PHY scenarios and any application involving a DFE with the need for minimum error propagation. Taught herein is a combined weighted DFE with erasure provision and interference removal in an optional two step mechanism. An article comprising a computer storage medium to execute the DFE design method is also disclosed.

Abstract: A system for receiving and handling a scrambled input data signal that includes a preamble with a start of frame delimiter (SFD) initiates an SFD search on the scrambled input data, thereby attempting to save an initialization period. The initialization period may be of the order of 7 uS, and its saving results in improved timeline management enabling antenna diversity and the possible use of high performance algorithms. The system may use two parallel paths for signal processing, each having an SFD detector and a descrambler. If the detected SFD is short, then the second path is disabled, and if it is long, then the first parallel path is disabled. Alternatively, the first path can be used for a finite period of time (for e.g., 40 symbols) and if the SFD is still not detected, the first path is disabled, and the system uses only the second path.

Abstract: A method of managing a processing system that has at least one processor, uses the steps of: measuring MCPS (million cycles per second) utilization in the at least one processor; estimating a cycle count requirement for an algorithm on least one processor based on measured MCPS utilization; and, estimating an ability to run multiple applications on the at least one processor by assessing MCPS requirements and estimated cycle count requirement. Measurement of the MCPS utilization is preferably done by using the steps of: choosing a critical path in the processor, e.g., by taking hard real time requirements into consideration; measuring time taken for processing along said critical path; and, calculating MCPS requirements along said critical path using the measured time taken and a current processor clock speed. The inventive method has application in 802.11 MAC. Also described is a programmed storage medium to execute the described method.