Abstract: A memory controller mechanism is operable in a first mode and a second mode. In the first mode, a first memory controller portion of the mechanism can use a first set of data terminals to perform a first external bus access operation (EBAO) and a second memory controller portion of the mechanism can use a second set of data terminals to perform a second EBAO. The first and second EBAO operations may be narrow accesses that occur simultaneously. In the second mode, one of the controllers can use both the first and second sets of data terminals to perform a wider third EBAO. The memory controller mechanism can dynamically switch between first mode and second mode operations. In situations in which one of the sets of data terminals would not otherwise be used, performing wide accesses in the second mode using the one set of data terminals improves bus utilization.

Abstract: A F/2F waveform generator has a comparator and an analog multiplexer. In a low-cost magnetic card reader application, a magnetic track signal is amplified, filtered, and compared with a threshold signal to create a digital signal output. The analog multiplexer detects changes in state of the digital signal. When a change of state is detected, the analog multiplexer switches among dynamically tunable threshold signals. The selected threshold signal is used for comparison with the magnetic track signal. Switching level detection enables accurate F/2F waveform generation from relatively noisy magnetic track signals, thus improving the robustness of magnetic card readers. The analog implementation eliminates the need for expensive A/D conversion and processing and the design can be readily implemented in a very compact and low-cost package.

Abstract: A general purpose BGA security cap includes a substrate, an integrated circuit die, and an array of bond balls. The substrate includes an anti-tamper security mesh of conductors. The bond balls include outer bond balls and inner bond balls that are fixed to the underside of the substrate. The integrated circuit drives and monitors the anti-tamper security mesh and communicates data using a serial physical interface through a subset of the inner bond balls. In one example, a user has circuitry to be protected. The user purchases the BGA security cap and fits it over the circuitry to be protected such that the integrated circuit of the security cap communicates tamper detect condition information via the serial interface to the underlying protected circuitry and causes sensitive information to be erased or a program to be halted in the event of a tamper condition.

Abstract: A system involves a plurality of RF-enabled occupancy detectors. Each occupancy detector communicates with and controls an associated plurality of RF-enabled fluorescent lamp starter units. A network master has an RF transceiver used to communicate with the occupancy detectors using a first protocol, thereby retrieving status information from the starter units. The network master also has a second RF transceiver for communicating directly with a cellular telephone using a second protocol. A user can use the cellular telephone to control and interact with the lighting system through the network master, and/or to retrieve status information from the network master. The network master automatically generates and sends email alerts to the user by sending the alerts to an email server. The email server forwards the emails to the cellular telephone via a cellular telephone network. Alerts may, for example, indicate a low battery voltage condition or that a lamp needs replacement.

Abstract: A low-power wireless network involves a master and a plurality of RF-enabled fluorescent lamp starter units. In each of a plurality of intervals, a starter wakes up and listens for a beacon, regardless of whether a beacon is transmitted during that interval or not. The starter operates in a low power sleep mode during the majority of the interval. The master can transmit during the beacon slot time of any interval, but typically only transmits frequently enough to maintain starter synchronization. If the master wishes to communicate with the starters with reduced latency, then the master can transmit a beacon in the next interval. Beacon slot time is varied within the interval (for example, from interval to interval or from group of intervals to group of intervals) in a pseudo-random time-hopping fashion known to both the starters and the master, thereby reducing persistence of collisions with similar networks.

Abstract: A system involves a plurality of RF-enabled occupancy detectors. Each occupancy detector communicates with and controls an associated plurality of RF-enabled fluorescent lamp starter units. A network master has an RF transceiver used to communicate with the occupancy detectors using a first protocol, thereby retrieving status information from the starter units. The network master also has a second RF transceiver for communicating directly with a cellular telephone using a second protocol. A user can use the cellular telephone to control and interact with the lighting system through the network master, and/or to retrieve status information from the network master. The network master automatically generates and sends email alerts to the user by sending the alerts to an email server. The email server forwards the emails to the cellular telephone via a cellular telephone network. Alerts may, for example, indicate a low battery voltage condition or that a lamp needs replacement.

Abstract: A wall plug power monitor accurately measures power consumption of an appliance connected via a wall plug power monitor to AC power supplies of any of the various frequencies used around the world. A three milliohm current sense resistor minimizes power consumption caused by current sensing. Digital oversampling and filtering methods allow for accurate calculation of voltage, current, and power consumption despite line noise and a minimized current sense resistor. Voltage sampling timed to correspond to positive-voltage pulses of voltage measurement signals and current sampling independently timed to correspond to positive-voltage pulses of current measurement signals allow the wall plug power monitor to be used with AC power supplies of varied and varying frequencies. A bit reservation system that scales values to preserve least significant digits allows accuracy while using an inexpensive integer-based processor.

Abstract: A system involves a plurality of RF-enabled occupancy detectors. Each occupancy detector communicates with and controls an associated plurality of RF-enabled fluorescent lamp starter units. A network master has an RF transceiver used to communicate with the occupancy detectors using a first protocol, thereby retrieving status information from the starter units. The network master also has a second RF transceiver for communicating directly with a cellular telephone using a second protocol. A user can use the cellular telephone to control and interact with the lighting system through the network master, and/or to retrieve status information from the network master. The network master automatically generates and sends email alerts to the user by sending the alerts to an email server. The email server forwards the emails to the cellular telephone via a cellular telephone network. Alerts may, for example, indicate a low battery voltage condition or that a lamp needs replacement.

Abstract: An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.

Abstract: A memory controller mechanism is operable in a first mode and a second mode. In the first mode, a first memory controller portion of the mechanism can use a first set of data terminals to perform a first external bus access operation (EBAO) and a second memory controller portion of the mechanism can use a second set of data terminals to perform a second EBAO. The first and second EBAO operations may be narrow accesses that occur simultaneously. In the second mode, one of the controllers can use both the first and second sets of data terminals to perform a wider third EBAO. The memory controller mechanism can dynamically switch between first mode and second mode operation. In situations in which one of the sets of data terminals would not otherwise be used, performing wide accesses in the second mode using the one set of data terminals improves bus utilization.

Abstract: An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.

Abstract: An internal precision oscillator (IPO) is trimmed within a microcontroller integrated circuit. The microcontroller integrated circuit receives a test program into flash memory on the microcontroller integrated circuit from a tester. The microcontroller integrated circuit also receives a reference signal from the tester. The IPO generates a clock signal having a frequency that depends upon a trim value. A general purpose timer on the microcontroller integrated circuit counts the number of cycles of the clock signal during a time period defined by the reference signal and outputs a digital value. A processor on the microcontroller integrated circuit executes the test program, reads the digital output, and adjusts the trim value such that the frequency of the clock signal is calibrated with respect to the reference signal. Test-time on the tester is reduced because the decision making during the frequency trimming process is made by the processor instead of the tester.

Abstract: Upon execution of an interrupt return (IRET) instruction when a second interrupt is pending, rather than popping a stack, obtaining processor state information, and then pushing the state information back onto the stack prior to vectoring off to a second interrupt service routine, direct vectoring is employed such that the stack is not pushed or popped but rather the processor vectors directly from the IRET instruction in the first interrupt service routine to the second interrupt service routine. A novel stored interrupt enable (SIE) bit stores whether maskable interrupts were enabled at the time the first interrupt service routine was entered. Execution of IRET automatically checks the SIE. If the SIE indicates interrupts were enabled, then direct vectoring occurs. If the SIE indicates that interrupts were disabled, then the second interrupt remains pending, and an interrupt return operation is performed by popping the stack and restoring the prior processor state.

Abstract: A microcontroller determines the position of the rotor of a brushless, direct-current motor by determining the time of zero crossing of back electromotive force (EMF) emanating from the non-driven phase winding. The zero crossing point is determined by interpolating voltage differentials that are time stamped. Each voltage differential is the difference between the phase voltage of the phase winding and the motor neutral point voltage. The time of zero crossing is determined without using a comparator and without interrupting the processor at each zero crossing point. The processor interpolates the time of zero crossing independently of when the zero crossing point occurs. A hold signal conductor is connected both to a sample and hold circuit and to the load input lead of a time stamp register. The microcontroller simultaneously captures a phase voltage in the sample and hold circuit and a timer count in the time stamp register.

Abstract: A method of fabricating a high-performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used, such as a Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) or other Anti-Reflective Coatings (ARCS), such as a conductive film like TiN. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. A Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition.

Abstract: The infrared LED of an IrDA module transmits IR energy with a peak wavelength (for example, 875 nm) appropriate for IrDA communication. This peak wavelength is lower than is the wavelength (for example, 940 nm) used in ordinary IR remote controls (RC). The IrDA LED does, however, transmit some energy at the wavelength of the peak sensitivity of an RC receiver. When making an IrDA transmission, the IrDA LED is driven with a lower amount of current. When making an RC transmission, the IrDA LED is driven with an increased amount of current such that higher wavelength emissions received by the RC receiver are of adequate power to realize RC communication. A passive circuit is disclosed for automatically increasing IrDA LED current during RC transmissions. The circuit involves an inductor that shunts current around a current-limiting resistor used to limit LED drive current.

Abstract: An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.

Abstract: A clock input filter uses a first programmable low-pass delay element to filter during a low period of an input clock signal and to output a SET signal. The clock input filter uses a second programmable low-pass delay element to filter during a high period of the input clock signal and to output a RESET signal. A latch is set and reset by the SET and RESET signals. The latch outputs a filtered version of the input signal that has the same approximate duty cycle as the input signal. A pair of gates generates a corresponding pair of duty cycle adjusted versions of the input signal. Output multiplexing circuitry is provided to output either the output of the latch, or an increased duty cycle version of the input signal, or a decreased duty cycle version of the input signal, or an unfiltered version of the input signal.

Abstract: A general purpose BGA security cap includes a substrate, an integrated circuit die, and an array of bond balls. The substrate includes an anti-tamper security mesh of conductors. The bond balls include outer bond balls and inner bond balls that are fixed to the underside of the substrate. The integrated circuit drives and monitors the anti-tamper security mesh and communicates data using a serial physical interface through a subset of the inner bond balls. In one example, a user has circuitry to be protected. The user purchases the BGA security cap and fits it over the circuitry to be protected such that the integrated circuit of the security cap communicates tamper detect condition information via the serial interface to the underlying protected circuitry and causes sensitive information to be erased or a program to be halted in the event of a tamper condition.

Abstract: Clock multiplexing techniques generate an output clock signal by detecting edges of a selected input clock signal and toggling the output clock signal based on detected edges of the selected input clock signal. Toggle signals are generated based on detected edges of the selected input clock signal. Toggle signals are used to control when the output clock signal is to toggle high or low. A latch holds the state of the output clock signal in its current state until changed by receipt of a toggle signal. Switching from use of a first clock signal to use of a second clock signal occurs regardless of whether the first input clock is operating. A delay is introduced that prevents glitches in the output clock signal that are less than one half clock period of the next selected input clock signal in duration.