Patents Assigned to J-DEVICES CORPORATION
  • Patent number: 10256196
    Abstract: A semiconductor device in which an insulating material layer contains no reinforced fibers such as a glass cloth or a nonwoven cloth and which enables miniaturization of metal thin-film wiring layers, a reduction in the diameter of metal vias, and a reduction in interlayer thickness. The semiconductor device includes an insulating material layer including one or more semiconductor elements sealed with an insulating material containing no reinforced fibers, a plurality of metal thin-film wiring layers, metal vias that electrically connect the metal thin-film wiring layers together and electrodes of the semiconductor elements and the metal thin-film wiring layers together, and a warpage adjustment layer arranged on one principal surface of the insulating material layer to offset warpage of the insulating material layer to reduce warpage of the semiconductor device.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: April 9, 2019
    Assignee: J-DEVICES CORPORATION
    Inventors: Kiminori Ishido, Michiaki Tamakawa, Toshihiro Iwasaki
  • Patent number: 10236231
    Abstract: A semiconductor device includes a lead frame; a circuit board located on the lead frame; a power device that includes a switching element and is mounted on the circuit board via a bump located between the power device and the circuit board; and a heat releasing member connected to the power device. The circuit board may be a multi-layer wiring board. The circuit board may include a capacitor element, a resistor element, an inductor element, a diode element and a switching element.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: March 19, 2019
    Assignee: J-DEVICES CORPORATION
    Inventors: Takeshi Miyakoshi, Sumikazu Hosoyamada, Yoshikazu Kumagaya, Tomoshige Chikai, Shingo Nakamura, Hiroaki Matsubara, Shotaro Sakumoto
  • Patent number: 10224256
    Abstract: A manufacturing method of a semiconductor package includes etching a first surface and a side surface of a base substrate, the base substrate including the first, a second and the side surfaces positioned between the first and the second surfaces, the base substrate containing a metal, attaching a metal different from the metal contained in the base substrate to the first and the side surfaces, disposing a semiconductor device on the second surface, the semiconductor device having an external terminal, forming a resin insulating layer sealing the semiconductor device, forming a first conductive layer on the resin insulating layer, forming an opening, exposing the external terminal, in the first conductive layer and the resin insulating layer; and forming a metal layer on the first and the side surfaces, on the first conductive layer and in the opening.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 5, 2019
    Assignee: J-DEVICES CORPORATION
    Inventors: Hirokazu Machida, Kazuhiko Kitano
  • Patent number: 10157760
    Abstract: A semiconductor manufacturing apparatus comprises a stage connected to a vacuum generator to suction a semiconductor wafer including a plurality of semiconductor chips, a suction control unit connected to a connecting portion of the stage and the vacuum generator to control the connection of the stage and the vacuum generator, a pickup unit connected to a movement control unit simultaneously picking up the plurality of semiconductor chips, and a control unit controlling movement and rotation of the pickup unit and controlling the suction control unit, the control unit is connected to the movement control unit. The pickup unit converts an interval of the plurality of semiconductor chips to a predetermined pitch and holds the pitch. The pickup unit moves the plurality of semiconductor chips from the stage to mounting positions of a supporting substrate and simultaneously adheres the plurality of semiconductor chips at the mounting positions by the control unit.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: December 18, 2018
    Assignee: J-DEVICES CORPORATION
    Inventor: Minoru Kai
  • Patent number: 10134710
    Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: November 20, 2018
    Assignee: J-DEVICES CORPORATION
    Inventors: Takeshi Miyakoshi, Sumikazu Hosoyamada, Yoshikazu Kumagaya, Tomoshige Chikai, Shingo Nakamura, Hiroaki Matsubara, Shotaro Sakumoto
  • Patent number: 10096564
    Abstract: A manufacturing method of a semiconductor package includes locating, on a substrate, a semiconductor device having an external terminal provided on a top surface thereof, forming a resin insulating layer covering the semiconductor device, forming an opening, exposing the external terminal, in the resin insulating layer, performing plasma treatment on a bottom surface of the opening, performing chemical treatment on the bottom surface of the opening after the plasma treatment, and forming a conductive body to be connected with the external terminal exposed in the opening.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: October 9, 2018
    Assignee: J-DEVICES CORPORATION
    Inventors: Toshiyuki Inaoka, Atsuhiro Uratsuji
  • Patent number: 10090276
    Abstract: A semiconductor package includes a first semiconductor device provided on a support substrate; a first encapsulation material covering the first semiconductor device; a first line provided on the first encapsulation material, the first line being connected with the first semiconductor device; an intermediate buffer layer covering the first line, and a second encapsulation material provided on the intermediate buffer layer. The first encapsulation material and the second encapsulation material are each formed of an insulating material different from an insulating material used to form the intermediate buffer layer. A second semiconductor device covered with the second encapsulation material may be provided on the intermediate buffer layer.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: October 2, 2018
    Assignee: J-DEVICES CORPORATION
    Inventor: Kiyoaki Hashimoto
  • Patent number: 10079161
    Abstract: An object of the present invention is to provide a semiconductor package with which it is possible to reduce a volume of an encapsulation resin and to easily embed a resin regardless of thicknesses of semiconductor chips and a small distance between adjacent semiconductor chips, as well as to provide a thin semiconductor package with which a final product includes no support flat plate. To realize this, a semiconductor package having a structure wherein semiconductor chips are accommodated in cavity parts of a support which is formed by copper plating and includes the cavity parts is provided.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: September 18, 2018
    Assignee: J-DEVICES CORPORATION
    Inventors: Toshiyuki Inaoka, Yuichiro Yoshikawa, Atsuhiro Uratsuji, Katsushi Yoshimitsu
  • Patent number: 10062638
    Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: August 28, 2018
    Assignee: J-DEVICES CORPORATION
    Inventor: Masafumi Suzuhara
  • Patent number: 9922931
    Abstract: An interconnect structure in which the current capacity of an interconnect pattern involving a large amount of current is increased without preventing the miniaturization of signal lines and increasing the film thickness. The interconnect structure includes a resin layer; and interconnects formed on the resin layer, wherein the resin layer has a plurality of parallel grooves in an area in which the interconnects are formed, and the interconnects are formed of a plating film created on a resin layer front surface in the area, in which the interconnects are formed, and on inner wall surfaces of the plurality of grooves.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: March 20, 2018
    Assignee: J-DEVICES CORPORATION
    Inventors: Hiroaki Matsubara, Tomoshige Chikai, Naoki Hayashi, Toshihiro Iwasaki
  • Patent number: 9905536
    Abstract: A semiconductor device is provided including a package substrate, and a plurality of semiconductor chips stacked above the package substrate, at least one of the plurality of semiconductor chips including a step part in a periphery edge part of a rear surface.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: February 27, 2018
    Assignee: J-DEVICES CORPORATION
    Inventor: Makoto Moda
  • Publication number: 20170301599
    Abstract: A semiconductor device includes a lead frame; a circuit board located on the lead frame; a power device that includes a switching element and is mounted on the circuit board via a bump located between the power device and the circuit board; and a heat releasing member connected to the power device. The circuit board may be a multi-layer wiring board. The circuit board may include a capacitor element, a resistor element, an inductor element, a diode element and a switching element.
    Type: Application
    Filed: June 30, 2017
    Publication date: October 19, 2017
    Applicant: J-DEVICES CORPORATION
    Inventors: Takeshi MIYAKOSHI, Sumikazu HOSOYAMADA, Yoshikazu KUMAGAYA, Tomoshige CHIKAI, Shingo NAKAMURA, Hiroaki MATSUBARA, Shotaro SAKUMOTO
  • Patent number: 9786611
    Abstract: A semiconductor package includes a support substrate; a stress relaxation layer provided on a main surface of the support substrate; a semiconductor device located on the stress relaxation layer; an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer; a line running through the encapsulation material and electrically connected to the semiconductor device; and an external terminal electrically connected to the line. Where the support substrate has an elastic modulus of A, the stress relaxation layer has an elastic modulus of B, and the encapsulation material has an elastic modulus of C under a same temperature condition, the relationship of A>C>B or C>A>B is obtained.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: October 10, 2017
    Assignee: J-DEVICES CORPORATION
    Inventors: Kiyoaki Hashimoto, Yasuyuki Takehara
  • Patent number: 9685376
    Abstract: A semiconductor device including: a support plate 1; a semiconductor chip 2 mounted on one principal surface of the support plate 1 via an adhesive layer, with the element circuit surface of the chip being directed upward; an insulation material layer 4 that seals the semiconductor chip 2 and the periphery of the semiconductor chip; openings formed on an electrode arranged on the element circuit surface of the semiconductor chip 2 in the insulation material layer 4; conductive portions 6 formed in the openings so as to be connected to the electrode of the semiconductor chip; a wiring layer 5 formed on the insulation material layer 4 so as to be connected to the conductive portions 6 and partially extending to the peripheral region of the semiconductor chip 2; and external electrodes 7 formed on the wiring layer 5.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: June 20, 2017
    Assignee: J-DEVICES CORPORATION
    Inventors: Yoshihiko Ikemoto, Hiroshi Inoue, Kiminori Ishido, Hiroaki Matsubara, Yukari Imaizumi
  • Publication number: 20170148766
    Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.
    Type: Application
    Filed: February 2, 2017
    Publication date: May 25, 2017
    Applicant: J-DEVICES CORPORATION
    Inventors: Takeshi MIYAKOSHI, Sumikazu HOSOYAMADA, Yoshikazu KUMAGAYA, Tomoshige CHIKAI, Shingo NAKAMURA, Hiroaki MATSUBARA, Shotaro SAKUMOTO
  • Patent number: 9635762
    Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: April 25, 2017
    Assignee: J-DEVICES CORPORATION
    Inventors: Shinji Watanabe, Sumikazu Hosoyamada, Shingo Nakamura, Hiroshi Demachi, Takeshi Miyakoshi, Tomoshige Chikai, Kiminori Ishido, Hiroaki Matsubara, Takashi Nakamura, Hirokazu Honda, Yoshikazu Kumagaya, Shotaro Sakumoto, Toshihiro Iwasaki, Michiaki Tamakawa
  • Patent number: 9627289
    Abstract: The present invention is to provide a semiconductor device in which the generation of the eddy current in a metal flat plate is reduced, and the Q value of the RF circuit of the semiconductor device is improved even using the metal flat plate as a support.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: April 18, 2017
    Assignee: J-DEVICES CORPORATION
    Inventors: Yoshihiko Ikemoto, Shigenori Sawachi, Fumihiko Taniguchi, Akio Katsumata
  • Patent number: 9601450
    Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: March 21, 2017
    Assignee: J-DEVICES CORPORATION
    Inventors: Takeshi Miyakoshi, Sumikazu Hosoyamada, Yoshikazu Kumagaya, Tomoshige Chikai, Shingo Nakamura, Hiroaki Matsubara, Shotaro Sakumoto
  • Patent number: 9553052
    Abstract: A magnetic shielding package of a non-volatile magnetic memory element, including: a soft magnetic material support plate 12; a first insulating material layer 13 formed on the support plate; a non-volatile magnetic memory element 11 fixed on the first insulating material layer; a second insulating material layer 14 that encapsulates the memory element and the periphery thereof; in the second insulating material layer, a wiring layer 15, a soft magnetic layer 15b or 25 and a conductive portion 16 connecting an electrode of the circuit surface of the memory element and the wiring layer; and a magnetic shield part 17 containing a soft magnetic material arranged like a wall at a distance from a side surface of the memory element so as to surround the memory element side surface partially or entirely, the magnetic shield part being magnetically connected to the soft magnetic layer.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: January 24, 2017
    Assignee: J-DEVICES CORPORATION
    Inventors: Hiroaki Matsubara, Toshihiro Iwasaki, Tomoshige Chikai, Kiminori Ishido, Shinji Watanabe, Michiaki Tamakawa
  • Patent number: 9418944
    Abstract: A semiconductor package includes a support substrate; a stress relaxation layer provided on a main surface of the support substrate; a semiconductor device located on the stress relaxation layer; an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer; a line running through the encapsulation material and electrically connected to the semiconductor device; and an external terminal electrically connected to the line. Where the support substrate has an elastic modulus of A, the stress relaxation layer has an elastic modulus of B, and the encapsulation material has an elastic modulus of C under a same temperature condition, the relationship of A>C>B or C>A>B is obtained.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: August 16, 2016
    Assignee: J-DEVICES CORPORATION
    Inventors: Kiyoaki Hashimoto, Yasuyuki Takehara