Patents Assigned to Japan Electronic Industry Development Association
  • Patent number: 4772099
    Abstract: A liquid crystal display device comprises a sandwich structure of support plates with a layer of liquid crystal filled therebetween. One support plate has an array of thin film transistors and thin film capacitors both formed thereon, while the other support plate has a counter electrode formed thereon. One of a pair of electrodes of each thin film capacitor on the one support plate is offset from the counter electrode at any area other than area where they form an effective capacitance element, the other the area where they form an effective capacitance element, the other capacitor electrodes serving as display electrodes.
    Type: Grant
    Filed: October 1, 1981
    Date of Patent: September 20, 1988
    Assignees: Sharp Kabushiki Kaisha, Japan Electronic Industry Development Association
    Inventors: Hiroaki Kato, Keisaku Nonomura, Kohhei Kishi, Tomio Wada
  • Patent number: 4654959
    Abstract: A thin film transistor comprises an insulating substrate, a semiconductor layer on the substrate, an electrically insulating oxide layer overlaying the semiconductor layer, and an electroconductive layer overlaying the oxide layer. The oxide layer is formed by oxidizing a portion of the semiconductor through a patterned opening in a photo resist. A method for the manufacture of the same is also disclosed.
    Type: Grant
    Filed: April 17, 1986
    Date of Patent: April 7, 1987
    Assignees: Sharp Kabushiki Kaisha, Japan Electronic Industry Development Association
    Inventors: Yutaka Takafuji, Hiroaki Kato, Fumiaki Funada
  • Patent number: 4469568
    Abstract: A method for making a thin-film transistor wherein a gate insulating layer is formed by anodizing two oxide layers on the substrate and then etching the assembly to completely remove the uppermost one of these layers to leave the lowermost layer so as to serve as the gate insulating layer.
    Type: Grant
    Filed: December 1, 1982
    Date of Patent: September 4, 1984
    Assignees: Sharp Kabushiki Kaisha, Japan Electronic Industry Development Association
    Inventors: Hiroaki Kato, Kohhei Kishi, Yutaka Takafuji
  • Patent number: 4464647
    Abstract: A sintered body for a humidity sensor is formed by baking a blend at 1,000.degree. to 1,400.degree. C., the blend comprising ZnO, Cr.sub.2 O.sub.3, V.sub.2 O.sub.5 and M.sub.2 O where M.sub.2 O is at least one metal oxide selected from Li.sub.2 O, Na.sub.2 O and K.sub.2 O. A pair of electrodes are each attached to the corresponding surface of the sintered body to obtain a humidity sensor of metal oxide which is relatively low in its resistive value and stable in its aging characteristic.
    Type: Grant
    Filed: January 25, 1982
    Date of Patent: August 7, 1984
    Assignees: Marcon Electronics Co. Ltd., Japan Electronic Industry Development Association
    Inventors: Yuji Yokomizo, Keiji Yuuki, Naoe Watanabe
  • Patent number: 4451554
    Abstract: A method of forming a thin-film pattern such as a thin-film circuit component comprises successive formation of a first metal layer and then a photo resist layer on a substrate by the utilization of a photoetching technique. The substrate having the first metal layer and the photo resist layer on the top of the first metal layer is deposited with second metal layers which are discontinued from each other, one of the second metal layers being deposited on the top of the photo resist layer while the other of the second metal layers is deposited directly on the substrate around the first metal layer. The substrate assembly is then immersed into a solvent bath to remove the photo resist layer together with the second metal layer resting thereon and is thereafter immersed into an etchant bath to remove the first metal layer, leaving the second metal layer on the substrate.
    Type: Grant
    Filed: July 30, 1982
    Date of Patent: May 29, 1984
    Assignees: Sharp Kabushiki Kaisha, Japan Electronic Industry Development Association
    Inventors: Kohhei Kishi, Hiroaki Kato, Masataka Matsuura, Tomio Wada
  • Patent number: 4425572
    Abstract: A thin film transistor comprising a substrate having source and drain electrodes formed thereon, a semiconductor layer making contact in part with the source electrode and in part with the drain electrode, a gate electrode, and a gate insulating layer positioned between the semiconductor layer and the gate electrode is disclosed. A portion of the drain electrode is held in overlapping relation to a portion of the gate electrode while a portion of the source electrode is spaced apart from said gate electrode.
    Type: Grant
    Filed: May 7, 1981
    Date of Patent: January 10, 1984
    Assignees: Sharp Kabushiki Kaisha, Japan Electronic Industry Development Association
    Inventors: Yutaka Takafuji, Keisaku Nonomura, Sadatoshi Takechi, Tomio Wada