Abstract: An interleaved analog-to-digital conversion (ADC) system may have timing errors in a time domain that is corrected using phase compensation in a phase domain. The ADC system may include sub-ADCs, each receiving a clock signal, which is associated with a representation of a timing skew value, reflecting an undesired timing error. A mixer may have sub-mixers, each receiving a sub-ADC output signal and a compensated numerically controlled oscillator (NCO) value. A combiner may combine the sub-mixer output signals. A decimator may decimate the output of the combiner. Each timing skew value is in a time domain. A compensated NCO value is determined using a respective phase skew value. Each phase skew value is an offset value in phase and is not a value in time. Each phase skew value in a phase domain compensates the respective timing skew value in a time domain. Multiple ADC systems and methods are described.

Abstract: An interleaved analog-to-digital conversion (ADC) system may have timing errors in a time domain that is corrected using phase compensation in a phase domain. The ADC system may include sub-ADCs, each receiving a clock signal, which is associated with a representation of a timing skew value, reflecting an undesired timing error. A mixer may have sub-mixers, each receiving a sub-ADC output signal and a compensated numerically controlled oscillator (NCO) value. A combiner may combine the sub-mixer output signals. A decimator may decimate the output of the combiner. Each timing skew value is in a time domain. A compensated NCO value is determined using a respective phase skew value. Each phase skew value is an offset value in phase and is not a value in time. Each phase skew value in a phase domain compensates the respective timing skew value in a time domain. Multiple ADC systems and methods are described.

Abstract: A band-pass clock distribution circuit includes a clock tree circuit including at least one clock buffer circuit. The clock tree circuit may be configured to receive a first clock signal from a clock generator circuit and to generate a second clock signal based on the first clock signal. A band-pass filter may be configured to receive the second clock signal and to provide a third clock signal to one or more load circuits. The band-pass filter includes a filtering resonant network including a first inductor and a second inductor coupled to one another at a center tap. The filtering resonant network is configurable to resonate with a parasitic capacitance associated with the one or more load circuits. A portion of the band-pass filter is integrated with the clock tree circuit.

Abstract: A band-pass clock distribution circuit includes a clock tree circuit including at least one clock buffer circuit. The clock tree circuit may be configured to receive a first clock signal from a clock generator circuit and to generate a second clock signal based on the first clock signal. A band-pass filter may be configured to receive the second clock signal and to provide a third clock signal to one or more load circuits. The band-pass filter includes a filtering resonant network including a first inductor and a second inductor coupled to one another at a center tap. The filtering resonant network is configurable to resonate with a parasitic capacitance associated with the one or more load circuits. A portion of the band-pass filter is integrated with the clock tree circuit.

Abstract: A millimeter-wave phase array system may include massive heterodyne transceivers as its building elements. A transceiver of each element may include an IQ image rejection heterodyne transmitter and a receiver. Each transmitter may include a single DAC, a Tx I channel, and a Tx Q channel. Each receiver may include an Rx I channel, an Rx Q channel, and a single ADC. For Tx IQ image rejection calibration, amplitude and phase offsets are determined, using both the Tx I and Tx Q channels from a first element and using only one of the Rx I or Rx Q channel from a second element. The IQ channel imbalances are compensated using the offsets in analog domain. A similar procedure is used for Rx IQ image rejection calibration with alternated signal path enabling. A frequency response variation of an RF front end is detected with a single path Tx/Rx channel setup.

Abstract: A hybrid digital-to-analog converter (DAC) driver circuit includes a current-mode DAC driver, a voltage-mode DAC driver, and a combination circuit. The current-mode DAC driver may be configured to receive a first set of bits of a digital input signal and to generate a first analog signal. The voltage-mode DAC driver may be configured to receive a second set of bits of the digital input signal and to generate a second analog signal. The combination circuit may be configured to combine the first analog signal and the second analog signal and to generate an analog output signal. The DAC driver circuit may be terminated by adjusting resistor values of the voltage-mode DAC driver. The current-mode DAC driver and the voltage-mode DAC driver are differential drivers, and may be configured to operate with a single clock signal.

Abstract: A DAC driver includes a number of DAC drivers coupled to a load network. A first DAC driver includes a first set of data switches that can be controlled by a first digital input signal. The first DAC driver further includes a first set of output switches, a first set of dump switches and a first set of current sources. Another DAC driver includes a second set of output switches, dump switches, and current sources. The first set of output switches or the second set of output switches are operable to respectively couple either one of the first set of data switches or the first set of current sources to the load network. The first set of dump switches or the second set of dump switches are operable to respectively dump the first set of current sources or the second set current sources into a respective dump load.

Abstract: A ultra-high speed DAC apparatus (e.g., with a full sampling frequency not less than 20 GHz) may include one or more digital pre-coders and DAC modules. Each DAC module may include multiple current-mode DAC systems and a first power combiner. The gate length of transistors within each DAC module may be between 6 and 40 nm. Each current-mode DAC system includes a transmission line (e.g., 40 to 80 microns long) coupled to multiple interleaving sub-DAC systems (within the current-mode DAC systems) and the first power combiner. The first power combiner combines, without interleaving, analog signals that have been interleaved within the current-mode DAC systems. The impedance of the first power combiner matches the impedance of each of the current-mode DAC systems and a load of the first power combiner. A second power combiner combines, without interleaving, analog signals from the DAC modules.

Abstract: A double-balanced radio-frequency (RF) mixing digital-to-analog converter (DAC) apparatus includes a load network, a first set of resistive DAC driver circuits and a first mixing core. The first mixing core can receive first RF input signals from the first set of resistive DAC driver circuits and can provide a first mixed signal to the load network. The first mixing core includes a first input differential pair coupled to two first cross-coupled differential pairs. The first input differential pair can receive first RF input signals at respective first input nodes. Each of the two first cross-coupled differential pairs can receive first positive and negative local oscillator (LO) signals at corresponding first input nodes. The first mixing core can mix the first RF input signals with the first positive and negative LO signals.

Abstract: A band-pass clock distribution circuit includes a clock tree circuit including at least one clock buffer circuit. The clock tree circuit may be configured to receive a first clock signal from a clock generator circuit and to generate a second clock signal based on the first clock signal. A band-pass filter may be configured to receive the second clock signal and to provide a third clock signal to one or more load circuits. The band-pass filter includes a filtering resonant network including a first inductor and a second inductor coupled to one another at a center tap. The filtering resonant network is configurable to resonate with a parasitic capacitance associated with the one or more load circuits. A portion of the band-pass filter is integrated with the clock tree circuit.

Abstract: A ultra-high speed DAC apparatus (e.g., with a full sampling frequency not less than 20 GHz) may include one or more digital pre-coders and DAC modules. Each DAC module may include multiple current-mode DAC systems and a first power combiner. The gate length of transistors within each DAC module may be between 6 and 40 nm. Each current-mode DAC system includes a transmission line (e.g., 40 to 80 microns long) coupled to multiple interleaving sub-DAC systems (within the current-mode DAC systems) and the first power combiner. The first power combiner combines, without interleaving, analog signals that have been interleaved within the current-mode DAC systems. The impedance of the first power combiner matches the impedance of each of the current-mode DAC systems and a load of the first power combiner. A second power combiner combines, without interleaving, analog signals from the DAC modules.

Abstract: A DAC driver includes a number of DAC drivers coupled to a load network. A first DAC driver includes a first set of data switches that can be controlled by a first digital input signal. The first DAC driver further includes a first set of output switches, a first set of dump switches and a first set of current sources. Another DAC driver includes a second set of output switches, dump switches, and current sources. The first set of output switches or the second set of output switches are operable to respectively couple either one of the first set of data switches or the first set of current sources to the load network. The first set of dump switches or the second set of dump switches are operable to respectively dump the first set of current sources or the second set current sources into a respective dump load.

Abstract: A multi-channel, multi-band system for wireless communication includes a radio frequency (RF) front end, a mixed-signal front end for converting an incoming analog RF signal into an incoming digital RF signal and converting a composite outgoing digital RF signal into an outgoing analog RF signal, a summation circuit for combining multiple outgoing digital RF signals to the composite outgoing digital RF signal, and multi-band transceivers. Each of the multi-band transceivers may process the incoming digital RF signal to provide an incoming baseband signal and process an outgoing baseband signal to provide an outgoing digital RF signal. The mixed-signal front end may apply a loading control to each transceiver for adjusting an amount of loading on the transmit path from the transceiver to the mixed-signal front-end. The transceivers may individually conduct a feedback calibration on the receive path to optimize the incoming baseband signal for each band.

Abstract: A hybrid digital-to-analog converter (DAC) driver circuit includes a current-mode DAC driver, a voltage-mode DAC driver, and a combination circuit. The current-mode DAC driver may be configured to receive a first set of bits of a digital input signal and to generate a first analog signal. The voltage-mode DAC driver may be configured to receive a second set of bits of the digital input signal and to generate a second analog signal. The combination circuit may be configured to combine the first analog signal and the second analog signal and to generate an analog output signal. The DAC driver circuit may be terminated by adjusting resistor values of the voltage-mode DAC driver. The current-mode DAC driver and the voltage-mode DAC driver are differential drivers, and may be configured to operate with a single clock signal.

Abstract: A DAC driver includes a number of DAC drivers coupled to a load network. A first DAC driver includes a first set of data switches that can be controlled by a first digital input signal. The first DAC driver further includes a first set of output switches, a first set of dump switches and a first set of current sources. Another DAC driver includes a second set of output switches, dump switches, and current sources. The first set of output switches or the second set of output switches are operable to respectively couple either one of the first set of data switches or the first set of current sources to the load network. The first set of dump switches or the second set of dump switches are operable to respectively dump the first set of current sources or the second set current sources into a respective dump load.