Abstract: Tools for ranking of generated properties are described. A plurality of circuit design properties are generated from a signal trace of the circuit design. A static analysis of the circuit design properties is performed against one or more circuit design constraints to determine whether the properties are true. Rankings for the circuit design properties are determined responsive to results of the static analysis. The ranking for a circuit design property represents a value of the circuit design property in validating correct functionality of the circuit design. At least some of the circuit design properties are presented in a user interface responsive to the rankings for the circuit design properties.

Abstract: A method for data propagation analysis. A data propagation diagram for a circuit design is generated. The data propagation diagram includes a plurality of nodes and a plurality of edges connecting the nodes. The nodes represent data locations in the circuit design and the edges represent data propagation paths between the data locations in the circuit design. A signal trace specifying signal values for the circuit design is analyzed to determine whether data at a first data location of the data locations during a first clock cycle is causally related to the data at a second data location of the data locations during a second clock cycle. A visual animation is displayed on the data propagation diagram indicating movement of the data between a first node of the nodes corresponding to the first data location and a second node of the nodes corresponding to the second data location.

Abstract: A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.

Abstract: A register transfer level (RTL) design is received which models a digital circuit in terms of the flow of digital signals. A power intent description is received which may include a description of power domains, identification of retention flops for each power domain, a list of isolation signals, and power switch definitions. A transformed RTL is produced accounting for functionality described in the power intent description. The transformed RTL includes flops designated as retention flops and non-retention flops. A retention flop module analyzes the flops to ensure that flops are properly designated as retention or non-retention flops. A verification module performs power aware sequential equivalence checking on various RTL and power intent descriptions to verify that RTL and power intent description outputs behave the same when accounting for power states.

Abstract: A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.

Abstract: A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.

Abstract: A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.

Abstract: A first waveform for a circuit design is received. The first waveform includes at least an actual value of a signal of the circuit design at one or more clock cycles. A user input for a cursor is received, and a signal wave overlay is displayed on the first waveform having an appearance corresponding to a location of the cursor. The signal wave overlay indicates a desired value of the signal at one or more clock cycles that is different than the actual value of the signal in the one or more clock cycles. Based on the desired value of the signal indicated by the signal wave overlay, a visualization constraint for the circuit design is generated. The visualization constraint is used to generate a second waveform, where the visualization constraint restricts the second waveform.

Abstract: A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.

Abstract: A first waveform for a circuit design is received. The first waveform includes at least an actual value of a signal of the circuit design at one or more clock cycles. A user input for a cursor is received, and a signal wave overlay is displayed on the first waveform having an appearance corresponding to a location of the cursor. The signal wave overlay indicates a desired value of the signal at one or more clock cycles that is different than the actual value of the signal in the one or more clock cycles. Based on the desired value of the signal indicated by the signal wave overlay, a visualization constraint for the circuit design is generated. The visualization constraint is used to generate a second waveform, where the visualization constraint restricts the second waveform.

Abstract: A register transfer level (RTL) design is received which models a digital circuit in terms of the flow of digital signals. A power intent description is received which may include a description of power domains, identification of retention flops for each power domain, a list of isolation signals, and power switch definitions. A transformed RTL is produced accounting for functionality described in the power intent description. The transformed RTL includes flops designated as retention flops and non-retention flops. A retention flop module analyzes the flops to ensure that flops are properly designated as retention or non-retention flops. A verification module performs power aware sequential equivalence checking on various RTL and power intent descriptions to verify that RTL and power intent description outputs behave the same when accounting for power states.

Abstract: The result of a property based formal verification analysis of a circuit design may include at least one counterexample for each property that is violated, which a user can use to debug the circuit design. To assist the user in this debugging process, a debugging tool applies one or more soft constraints to a counterexample trace that simplify the appearance of the trace when displayed as a waveform. The debugging tool thus facilitates a user's understanding of what parts of the counterexample trace are responsible for the property failure. Also described is a power analysis tool that increases the noise level of a trace for a circuit design in order to facilitate analysis of the circuit design's power characteristics.

Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

Abstract: A computer-implemented method and non-transitory computer readable medium for circuit design verification. Formal verification is performed on a circuit design to prove a correctness of a property of the circuit design. The circuit design has a cone of influence representing a portion of the circuit design capable of affecting signals of the property. A proof core of the circuit design is identified, the proof core being a portion of the cone of influence that is sufficient to prove the correctness of the property. A coverage metric is generated that is indicative of a level of formal verification coverage provided by the property based on the proof core of the circuit design.

Abstract: Tools for ranking of generated properties are described. A plurality of circuit design properties are generated from a signal trace of the circuit design. A static analysis of the circuit design properties is performed against one or more circuit design constraints to determine whether the properties are true. Rankings for the circuit design properties are determined responsive to results of the static analysis. The ranking for a circuit design property represents a value of the circuit design property in validating correct functionality of the circuit design. At least some of the circuit design properties are presented in a user interface responsive to the rankings for the circuit design properties.

Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

Abstract: A first signal trace is received including signal values satisfying a target event. A first trace signature is generated describing a portion of the first signal trace that causes the target event to occur. A second signal trace is generated that includes signal values satisfying the target event. A second trace signature is generated describing a portion of the second signal trace that causes the target event to occur. Differential signal events are determined that differentiate the first trace signature from the second trace signature. The differential signal events are events from the first signal trace that cause the target event to occur, but do not appear in the second trace signature. The process can be repeated to receive a plurality of signal traces, and to generate a plurality of signal traces. The differential signal events are indexed in a datastore in association with the signal traces.

Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

Abstract: An analysis tool that generates properties for a circuit design. The debugging tool receives a circuit design encoded in a hardware description language. The tool identifies portions of the circuit design that correspond to features of interest (e.g., counters, finite state machines, one hot vectors, etc) in the circuit design. Each portion of the circuit design has a cone of influence, and the tool identifies control signals from within the cones of influence. By identifying control signals in this manner, the tool can then generate the properties based on values for the control signals and the identified portions of the circuit design that are obtained from data describing the operation of the circuit design over a number of clock cycles (e.g., simulation data). The result is one or more properties that are likely to represent a relevant behavior of the circuit design.

Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.