Abstract: A verification system determines proof of the absence of a deadlock condition or other data-transport property in a multi-system SoC using helper assertions derived from a transaction definition. The verification system receives the circuit design information along with a transaction definition for one or more ports of the SoC. Once specified, the transaction definition is instantiated into the full system or subsystem RTL, generating an expanded RTL and a deadlock property. Data flow through the RTL is analyzed to extract helper assertions describing how the data flowed through the RTL. Helper assertions are automatically extracted to aid in the verification of the absence of a deadlock condition. Using the helper assertions, the formal engine applies one or more techniques to formally analyze the circuit design to prove the absence of a deadlock condition.

Abstract: A system and method for identifying, for a selected signal, those signals whose value is relevantly determined based upon a value of the selected signal, where a set of signals to be examined is identified as those signals that satisfy one or more of the following criteria: (1) they are RTL load signals of the selected signal, (2) they are RTL load signals that are also in an analysis region, (3) they are RTL load signals within the analysis region that also contribute to a proof target, and/or 4) they are RTL load signals that contribute to the proof target.

Abstract: A method and apparatus for measuring the progress of a formal verification process using an analysis region, and measures the effectiveness of the current set of properties/requirements in verifying different portions of logic within the design. The present invention applies the concept of analysis region to analyze the properties/requirements for a design. The analysis region can be expanded or contracted either manually or automatically based upon the results of the analysis. The present invention generates a visual display that is available to the user that represents the amount of source code in the analysis region for a given property or multiple properties in comparison to the maximum possible analysis region. The present invention can display this information in a bar graph format, on a line-by-line basis for the source code and on a waveform display, for example.

Abstract: The present invention is directed to a system and a method for verifying properties of a circuit model while providing information to help the user manually modify a design analysis region and/or environmental constraints. While conventional systems attempt to substantially automate the entire formal verification process, the present invention iteratively provides information to the user about the cost and effect of changes to the environmental constraints and the analysis region. This information enables the user to weigh the effectiveness and efficiency of one or more modifications to the design analysis area and/or to the environmental constraints (assumptions). The information provided to the user can help a user compare a variety of alternative modifications in order to select the modifications that are efficient and effective.