Abstract: A static formal verification tool is used to test properties for a circuit design, where the properties are written in a verification language, such as SystemVerilog, that allows local variables. The use of local variables presents implementation challenges for static formal verification tools because it requires multiple instances of the local variables to be tracked during the verification process. To deal with local variables, the static formal verification tool translates a property containing local variables into an optimized, statically allocated data structure that does not need multiple representation of different instances of the local variables. The formal verification is then performed using the data structure. This reduces the verification complexity and makes the size of the problem representation predictable.

Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

Abstract: The result of a property based formal verification analysis of a circuit design may include at least one counterexample for each property that is violated, which a user can use to debug the circuit design. To assist the user in this debugging process, a debugging tool displays the counterexample trace annotated in such a way to illustrate where the property violation occurs and what parts of this trace contributes to the property violation. The debugging tool thus facilitates understanding of what parts of the counterexample trace are responsible for the property failure. The user can then select any of those contributing points as a starting point for further debugging.

Abstract: In the field of functional verification of digital designs in systems that use an abstraction for portions of a circuit design to perform the verification proof, a tool is described for resolving inconsistencies between the design and abstractions for the design. The tool provides information to a user about intermediate steps in the verification process. In response, the user may provide insight about the design to allow the tool to adjust the verification analysis of the design. The information provided to the user, including possible conflicts between the design and its abstractions, may include visualization techniques to facilitate the user's understating of any inconsistencies.

Abstract: A counter abstraction tool generates an abstraction model for one or more counters in a circuit design for use with a formal verification system. The tool detects the presence of a counter in a circuit design, identifies one or more special values for the counter, and creates an abstraction for the counter. The tool can automatically perform the abstraction, guide a user in configuring the appropriate abstraction for the counter, or perform a combination of automatic and manual abstraction. The tool may further accommodate related counters.

Abstract: While performing functional verification on a circuit design, a verification tool allows a user to analyze the results of a previous functional analysis. The tool may also receive commands for a next verification analysis while performing a current analysis, and it may allow a user to abort a current analysis. Results from a completed analysis may be discarded or saved for viewing by a user while a next verification is performed on the circuit design. This allows a user to continue to debug and analyze the circuit design without having to wait until previous steps in the verification analysis are completed.

Abstract: A property used in functional verification of a circuit design is debugged independently of the circuit design for which the property is intended. Visualization of the property under various conditions helps a user to debug any errors in how the property is implemented in a requirements model. To visualize a particular property, a trace of a corresponding property in the requirements model is generated. The trace illustrates waveforms of a set of signals related to the property for a number of clock cycles. To visualize the property under various conditions, a user can find additional traces of the property by applying visualization constraints to obtain meaningful traces.

Abstract: A counter abstraction tool generates an abstraction model for one or more counters in a circuit design for use with a formal verification system. The tool detects the presence of a counter in a circuit design, identifies one or more special values for the counter, and creates an abstraction for the counter. The tool can automatically perform the abstraction, guide a user in configuring the appropriate abstraction for the counter, or perform a combination of automatic and manual abstraction. The tool may further accommodate related counters.

Abstract: To perform functional verification of a digital design that includes one or more datapaths, a formal verification system includes a datapath abstraction tool. The datapath abstraction tool detects a datapath in a circuit design and performs an appropriate abstraction of the datapath. The tool may also deduce datapath elements from identified ones as well as link the abstractions of particular datapath elements. The abstraction tool then passes the circuit design with the abstraction to the verification software to simplifying the formal verification process.

Abstract: A highlighting system for use with electronic circuit design tools is provided for displaying signal waveforms and Register Transfer Logic (RTL) source code portions corresponding to a selected signal in the same window. The user selects a time and signal to be explored. Based on the selected time and signal, the values of all related signals are identified from a database generated by simulation of RTL source code. Nodes corresponding to the related signals are identified from a gate-level netlist corresponding to the RTL source code and the nodes responsible for the particular value of the selected signal at selected time are identified. The nodes are then mapped on to the RTL source code portions by a process of Instrumentation. The RTL source code portions so identified are then displayed. In particular, the portions of the RTL source code responsible for the particular value or transition in particular value of the signal at the selected time are highlighted.

Abstract: The present invention is used for guiding formal verification of a circuit design in circuit simulation software to optimize the time required for verification of a circuit design. The invention modifies the analysis region being used for verification in order to optimize the time for verification. The invention allows for manual, semi-automatic, and automatic modification of the analysis region. The modification is done by either expanding or reducing the analysis region or by adding new rules as assumptions to the existing analysis region. The invention also uses the concept of an articulation point for modification of the analysis region. The modification of the analysis region is performed in a manner to optimize time and memory required for verification of the circuit design.

Abstract: Methodology for verifying properties of a circuit model in context of given environmental constraints is disclosed. Verification of a specified property is performed by analyzing only a portion of the circuit model. The present methodology is also directed towards reducing the computation time for verifying the specified property. Further, the present methodology allows the connection of an additional circuit model to the circuit model in a non-intrusive manner. The connection is made without making any modifications to the description of the circuit model. This permits the straightforward specification of related environmental constraints and properties, which makes it possible to verify correct behavior of complex interfaces.

Abstract: This invention determines whether two logic level circuit models have equivalent functionality. The method allows difficult portions of the equivalent functionality check to be partitioned and concurrently solved in a distributed computing environment. This permits the user to use, in a scalable fashion, additional computing resources to rapidly solve difficult equivalent functionality checks. The method allows difficult checks to be solved using (1) a divide-and-conquer approach, (2) by a competitive approach in which many independent attempts are made to solve the same check, or (3) by allocating more resources to solve the difficult check.