Abstract: A CMOS model generating apparatus 1 according to the present invention generates a CMOS model by converting an In-Ip space into an xn-xp space such that a typical condition TT and corner conditions FF, SS in the In-Ip space become (0, 0), (?, ?) and (??, ??) in the xn-xp space, determining an ellipse fitting to the respective mappings of the corner conditions FF, SS, FS and SF with the mapping (0, 0) of the typical condition TT as a center, expressing two independent principal components in the form of a Gaussian distribution using the major and minor axes of this ellipse as axes of the principal components, and obtaining a probability distribution determining deviations of the Gaussian distribution such that the cumulative probability within this ellipse becomes equal to the one presumed by the corner conditions FF, SS, FS and SF.

Abstract: In a preferred embodiment, a CPU extracts a regular structure in a layout of an integrated circuit using layout graphic information, net list information, and constraint information with reference to regularity information of an array-structure, a row-structure, and the like, stored in a magnetic disk storage to evaluate the regular structure, and optimizes the layout of the integrated circuit using the layout graphic information, the net list information, etc., in consideration of the evaluation of the regular structure. Thus, a layout excellent in circuit characteristics and device matching properties, wiring characteristics can be obtained.

Abstract: A CMOS model generating apparatus 1 according to the present invention generates a CMOS model by converting an In-Ip space into an xn-xp space such that a typical condition TT and corner conditions FF, SS in the In-Ip space become (0, 0), (?, ?) and (??, ??) in the xn-xp space, determining an ellipse fitting to the respective mappings of the corner conditions FF, SS, FS and SF with the mapping (0, 0) of the typical condition TT as a center, expressing two independent principal components in the form of a Gaussian distribution using the major and minor axes of this ellipse as axes of the principal components, and obtaining a probability distribution determining deviations of the Gaussian distribution such that the cumulative probability within this ellipse becomes equal to the one presumed by the corner conditions FF, SS, FS and SF.

Abstract: In a preferred embodiment, a CPU extracts a regular structure in a layout of an integrated circuit using layout graphic information, net list information, and constraint information with reference to regularity information of an array-structure, a row-structure, and the like, stored in a magnetic disk storage to evaluate the regular structure, and optimizes the layout of the integrated circuit using the layout graphic information, the net list information, etc., in consideration of the evaluation of the regular structure. Thus, a layout excellent in circuit characteristics and device matching properties, wiring characteristics can be obtained.