Abstract: Embodiments of the present invention provide a current mode logic circuit, comprising first and second differential switching stages, each stage arranged being arranged to receive a plurality of clock signals, such that the first and second differential switching stages respond to a combination of the plurality of clock signals.

Abstract: Apparatus for producing a signal, comprising a capacitor; a first current source for one of charging and discharging the capacitor over a first time period; a second current source for one of discharging and charging the capacitor over a first portion of a second time period; a detector for detecting when the voltage across the capacitor is substantially a first voltage and controlling the second current source for a second portion of the second time period to substantially maintain the voltage across the capacitor; and an apparatus output for indicating when the voltage across the capacitor is one of above and below the first voltage.

Abstract: There is provided a transceiver comprising a first node for receiving a received signal and transmitting a transmitted signal; a receiver, connected between a first voltage and the first node, for processing the received signal; a transmitter, connected between a second voltage and the first node, for generating the transmitted signal; and a DC voltage controller for selecting a DC component of a voltage of the first node to at least one of: selectively activate at least one of the transmitter and the receiver; and selectively substantially deactivate at least one of the transmitter and receiver.

Abstract: Embodiments of the invention consist in a method of carrier synchronization, comprising determining a frequency offset estimate from a rate of change of a phase difference between a local oscillator signal and a carrier signal of a received signal; and adjusting a frequency of the local oscillator signal by the frequency offset estimate.

Abstract: Embodiments of the present invention relate to a data processing system comprising a first arithmetic unit comprising at least one finite field multiplier and at least one finite field adder for selectively performing at least two finite field arithmetic calculations; the data processing system comprising means to use a previous finite field arithmetic calculation result in a current finite field arithmetic calculation to determine at least part of a polynomial.

Abstract: A transconductance control circuit, comprising: a test transconductance circuit for providing an output current from a reference voltage; apparatus for deriving a bias current for the test transconductance circuit from the output current, the bias current including a component that varies with temperature and a component that varies with process; and apparatus for providing the bias current to other transconductance circuits.

Abstract: A comparator, comprising at least one current stage for providing a first current proportional to a difference between first and second comparator inputs, the first current being provided to an amplifier input; an amplifier for amplifying a current provided to the amplifier input and providing a comparator output; apparatus for introducing hysteresis, comprising at least one of a current source and a current sink, the current source being arranged to selectively source a source current to the amplifier input such that the comparator output changes from a first state to a second state when a difference between the first and second inputs rises above a first value, and the current sink being arranged to selectively sink a sink current from the amplifier input such that the comparator output changes from the second state to the first state when the difference between the first and second inputs falls below a second value; and apparatus for controlling at least one of the source current and the sink current to be

Abstract: Apparatus for producing a signal, comprising a capacitor; a first current source for one of charging and discharging the capacitor over a first time period; a second current source for one of discharging and charging the capacitor over a first portion of a second time period; a detector for detecting when the voltage across the capacitor is substantially a first voltage and controlling the second current source for a second portion of the second time period to substantially maintain the voltage across the capacitor; and an apparatus output for indicating when the voltage across the capacitor is one of above and below the first voltage.

Abstract: A radio receiver is selectively operable in a current mode or a voltage mode according to conditions prevailing within a wireless environment. If the signal levels within the wireless environment are relatively low, the radio receiver is operable in current mode. If the signal levels within the wireless environment are relatively high, the radio receiver is operable in voltage mode. The radio receiver is switchable between current and voltage mode of operation via selectively actuable switches that bringing into effect or remove from effect corresponding resistances.

Abstract: Embodiments of the invention provide an analogue to digital converter comprising a dual differential digital to analogue converter (DAC) having first and second digital inputs for first and second digital input signals respectively, and having first and second analogue differential outputs for first and second differential output signals respectively, where the first and second digital output signals are associated with the first and second digital inputs respectively; storage for storing a DAC digital input value; logic for deriving the first and second digital input signals from the DAC digital input value, such that the difference between the first and second differential output signals from the DAC represents the DAC digital input value; a comparator for comparing the first and second differential output signals from the DAC with an analogue input signal and providing a comparator output; and a controller, responsive to the comparator output, for modifying the DAC digital input value such that the DAC dig

Abstract: There is provided a transceiver comprising a first node for receiving a received signal and transmitting a transmitted signal; a receiver, connected between a first voltage and the first node, for processing the received signal; a transmitter, connected between a second voltage and the first node, for generating the transmitted signal; and a DC voltage controller for selecting a DC component of a voltage of the first node to at least one of: selectively activate at least one of the transmitter and the receiver; and selectively substantially deactivate at least one of the transmitter and receiver.

Abstract: Embodiments of the invention consist in a method of carrier synchronization, comprising determining a frequency offset estimate from a rate of change of a phase difference between a local oscillator signal and a carrier signal of a received signal; and adjusting a frequency of the local oscillator signal by the frequency offset estimate.

Abstract: Embodiments of the present invention relates to an integrated mixer. A problem with producing low power consumption mixers is that they require a relatively high operating voltage due to the number of layers of transistor between the power rails.

Abstract: A method for generating at least one error checking code includes creating a modified input data word, including (k+m) bits, by combining an input data word, having n-bits, with at least a previously calculated at least one error checking code, including in-bits, where n?k, and calculating a first m-bit error checking code from at least a first selected portion of the modified input data word.

Abstract: The present invention relates to a folded differential amplifier having very high output impedance capable of being operated at frequencies of the order of gigahertz.