Abstract: A memory device includes several normal memory circuits and a redundant memory circuit is disclosed. The several normal memory circuits include several normal memory arrays. The redundant memory circuit includes a redundant memory array. The several normal memory arrays share the redundant memory array. When a first normal memory cell of a first normal memory array of the several normal memory arrays is destructed, a first redundant memory cell of the redundant memory array replaces the first normal memory cell. When a second normal memory cell of a second normal memory array of the several normal memory arrays is destructed, a second redundant memory cell of the redundant memory array replaces the second normal memory cell.

Abstract: A calibration device which is configured for calibrating a memory is provided. The calibration device includes an input terminal, a first pull-up circuit, and a first comparator. The input terminal is coupled to an external resistor. The first pull-up circuit is coupled to the input terminal, and configured to receive a power supply voltage. The first pull-up circuit includes a plurality of first pull-up units. The first pull-up units are coupled to each other in parallel. The first comparator is coupled to the input terminal. The first comparator is configured to receive a proportion voltage which is corresponding to the power supply voltage, and output a first control signal to the first pull-up units, such that a resistance of each of the first pull-up units is equal to a resistance of the external resistor.

Abstract: Artificial neuromorphic circuit includes synapse and post-neuron circuits. Synapse circuit includes phase change element and receives first and second pulse signals. Post-neuron circuit includes input, output and integration terminals. Integration terminal is charged to membrane potential according to first pulse signal. Post-neuron circuit further includes first and second control circuits, and first and second delay circuits. First control circuit generates firing signal at output terminal based on membrane potential. Second control circuit generates first control signal based on firing signal. First delay circuit delays firing signal to generate second control signal. Second delay circuit delays second control signal to generate third control signal.

Abstract: Artificial neuromorphic circuit includes synapse and post-neuron circuits. Synapse circuit includes phase change element, first switch having at least three terminals, and second switch. Phase change element includes first and second terminals. First switch includes first, second and control terminals. Second switch includes first, second and control terminals. First switch is configured to receive first pulse signal. Second switch is coupled to phase change element and first switch, and is configured to receive second pulse signal. Post-neuron circuit includes capacitor and input terminal. Input terminal of post-neuron circuit charges capacitor in response to first pulse signal. Post-neuron circuit generates firing signal based on voltage level of capacitor and threshold voltage. Post-neuron circuit generates control signal based on firing signal. Control signal controls turning on of second switch.

Abstract: A method of fabricating layered structure is disclosed. A basal layer is formed. A laminate is formed on the basal layer, and the laminate includes a device layer, a sacrificial layer and a protection layer stacked in sequence. The device layer, the sacrificial layer and the protection layer are etched to obtain a patterned laminate. A first dielectric layer covering a lateral surface of the patterned laminate is formed. Part of the first dielectric layer and part of the protection layer are removed by polishing. The protection layer of the patterned laminate is etched to expose the sacrificial layer. A through hole in the first dielectric layer is formed to expose the basal layer. The sacrificial layer of the patterned laminate is etched to form an opening in the first dielectric layer, and the opening exposes a top surface of the device layer.

Abstract: A phase change memory and a method of fabricating the same are provided. The phase change memory includes a lower electrode, an annular heater disposed over the lower electrode, an annular phase change layer disposed over the annular heater, and an upper electrode. The annular phase change layer and the annular heater are misaligned in a normal direction of the lower electrode. The upper electrode is disposed over the annular phase change layer, in which the upper electrode is in contact with an upper surface of the annular phase change layer. The present disclosure simplifies the manufacturing process of the phase change memory, reduces the manufacturing cost, and improves the manufacturing yield. In addition, a contact surface between the heater and the phase change layer of the phase change memory of the present disclosure is very small, so that the phase change memory has an extremely low reset current.

Abstract: Artificial neuromorphic circuit includes synapse circuit and post-neuron circuit. Synapse circuit includes phase change element, first switch, and second switch. First switch is coupled to phase change element, and is configured to receive first pulse signal. Second switch is coupled to phase change element. Input terminal of post-neuron circuit is coupled to switch circuit, and input terminal is coupled to phase change element. Input terminal charges capacitor through switch circuit in response to first pulse signal. Post-neuron circuit is configured to generate firing signal based on voltage level at input terminal and threshold voltage, and is further configured to generate first control signal and second control signal based on firing signal. Post-neuron circuit turns off switch circuit according to first control signal. Second control signal is configured to cooperate with second pulse signal to control second switch so as to control a state of phase change element.

Abstract: A memory device includes a memory group and a control circuit. The memory group includes several memory banks. The control circuit is coupled to the memory group. The control circuit includes a tri-state logic enable circuit and an address decoding circuit. The tri-state logic enable circuit is configured to temporarily store several temporarily stored address signals, to output the several temporarily stored address signals according to a synchronization signal, to decode the several temporarily stored address signals to generate an enable signal, and to transmit the enable signal to one of the several memory banks. The address decoding circuit is configured to decode the several temporarily stored address signals to drive the one of the several memory banks.

Abstract: Artificial neuromorphic circuit includes synapse circuit and post-neuron circuit. Synapse circuit includes phase change element, first switch, and second switch. Phase change element includes first terminal and second terminal. First switch includes first terminal and second terminal. Second switch includes first terminal, second terminal, and control terminal. First switch is configured to receive first pulse signal. Second switch is coupled to phase change element and first switch. Second switch is configured to receive second pulse signal. Post-neuron circuit includes capacitor and input terminal. Input terminal of post-neuron circuit charges capacitor in response to first pulse signal. Post-neuron circuit generates firing signal based on voltage level of capacitor and threshold voltage. Post-neuron circuit generates control signal based on firing signal. Control signal controls turning on of second switch.

Abstract: An operation method is applied to a memory device. The memory device includes a plurality of memory tiles. The operation method includes following steps: utilizing a first wear leveling process to perform an intra-tile wear leveling on the plurality of memory tiles by a processor; and utilizing a second wear leveling process to perform an inter-tile wear leveling on the plurality of memory tiles by the processor.

Abstract: A method of manufacturing a diode structure includes forming a first stack on a silicon layer on a substrate. A first sidewall spacer extending along and covering a sidewall of the first stack is formed. The silicon layer is selectively etched to a first predetermined depth, thereby forming a second stack. The remaining silicon layer includes a silicon base. A second sidewall spacer extending along and covering a sidewall of the second stack is formed. The silicon base is selectively etched to form a third stack on the substrate. With the second sidewall spacer as a mask, lateral plasma ion implantation is performed. Defects at the interface between two adjacent semiconductor layers can be reduced by the method.

Abstract: A mixed mode memory comprises a memory array, a word line decoder, an intermediary circuit and a reading and writing circuit, wherein the word line decoder is electrically coupled to the memory array, and the intermediary circuit is electrically coupled to the memory array and the writing circuit. The memory array comprises mixed mode memory cells with each cell comprising a reading and writing component group, a storage circuit and a selection circuit. The reading and writing component group is electrically coupled to a word line which controls the reading and writing component group to be conducted or not conducted, and electrically coupled to two bit lines which respectively transmit two data signals. The storage circuit generates two reading response signals based on a reading drive signal. The selection circuit controls the storage circuit to operate in a volatile or non-volatile storage mode based on a selection voltage.

Abstract: Disclosed is a memory drive device. The memory drive device comprises a control circuit, a reference voltage generation circuit, and a first switch. The control circuit is used to generate a first signal according to an input signal. The reference voltage generation circuit comprises a reference resistor and is used to generate a reference signal according to the first signal. The first switch is coupled to a memory resistor and is used to generate a drive signal according to the first signal so as to set a resistance value of the memory resistor. When the input signal is decreased and a resistance value of the memory resistor is greater than a resistance value of the reference resistor, the time when the drive signal is decreased is greater than the time when the reference signal is decreased.

Abstract: A method of manufacturing a phase change memory includes: forming a stacked structure including a conductive layer, a lower electrode layer over the conductive layer, an upper electrode layer, a phase change material between the lower and upper electrode layers, and a selector material between the conductive layer and the lower electrode layer; etching the upper electrode layer to form an upper electrode wire; etching the phase change material according to the upper electrode wire to form a phase change material layer and expose a portion of the lower electrode layer, wherein the phase change material layer has an exposed side surface; after etching the phase change material, performing a nitridizing treatment on the side surface of the phase change material layer to form a nitridized phase change material layer covering the same; and etching the lower electrode layer, the selector material and the conductive layer.

Abstract: A memory driving device, comprising a switch, a voltage setting circuit, and a bias control circuit. The switch is coupled to a memory at a node. The voltage setting circuit is coupled to the switch and configured to provide a set signal during a first period to turn on the switch, so as to generate current flowing through the switch to the memory unit. The bias control circuit is respectively coupled to the switch and the node, and, during a second period, continuously provides a bias signal to control the switch so as to adaptively adjust a value of the setting current of the switch. The configuration setting terminal is coupled to the voltage setting circuit and the bias control circuit to control the first and the second period.

Abstract: A method of manufacturing a phase change memory includes: forming a stacked structure including a conductive layer; a lower electrode layer over the conductive layer; an upper electrode layer over the lower electrode layer; and a phase change material between the lower and upper electrode layers; etching the upper electrode layer according to a first mask to form an upper electrode wire; simultaneously etching the phase change material according to the upper electrode wire and performing a nitridizing treatment in a same plasma etching chamber until a phase change material layer and a nitridized phase change material layer are formed beneath the upper electrode wire and a portion of the lower electrode layer is exposed, wherein the nitridized phase change material layer covers a side surface of the phase change material layer; and removing the portion of the lower electrode layer and the conductive layer therebeneath.

Abstract: A mixed mode memory comprises a memory array, a word line decoder, an intermediary circuit and a reading and writing circuit, wherein the word line decoder is electrically coupled to the memory array, and the intermediary circuit is electrically coupled to the memory array and the writing circuit. The memory array comprises mixed mode memory cells with each cell comprising a reading and writing component group, a storage circuit and a selection circuit. The reading and writing component group is electrically coupled to a word line which controls the reading and writing component group to be conducted or not conducted, and electrically coupled to two bit lines which respectively transmit two data signals. The storage circuit generates two reading response signals based on a reading drive signal. The selection circuit controls the storage circuit to operate in a volatile or non-volatile storage mode based on a selection voltage.

Abstract: A mixed mode memory cell comprises a reading and writing component group, a storage circuit and a selection circuit. The reading and writing component group is electrically coupled to a word line and two bit lines, wherein the two bit lines respectively transmit two data signals. The storage circuit is electrically coupled to the reading and writing component group. The selection circuit is electrically coupled to the reading and writing component group and the storage circuit, and configured to control the storage circuit to operate in a volatile storage mode or a non-volatile storage mode based on a selection voltage.

Abstract: A memory test array and a test method thereof are provided. The memory test array includes a first memory array, a second memory array, and a plurality of first common conductive pads. The first memory array includes a plurality of first bit lines and a plurality of first word lines. The second memory array is adjacent to the first memory array and includes a plurality of second bit lines and a plurality of second word lines. Each of the first common conductive pads has a first end and a second end, and the first ends and the second ends are respectively coupled to the first bit lines and the second bit lines, or respectively coupled to the first word lines and the second word lines. The memory test array of the present disclosure can effectively save the area of the memory test chip and make the test process more efficient.

Abstract: A memory driving device includes a first switch, a voltage detecting circuit, and a switch array. The first switch includes a first output terminal and a first control terminal, and the first output terminal provides an output voltage for a memory unit. The voltage detecting circuit is coupled to the first output terminal, and configured to detect the output voltage, and generates a control signal according to the output voltage, wherein the control signal changes in real time according to the changing of the output voltage. The switch array includes a plurality of second switches, and the second switches are coupled to the first control terminal. At least one of the second switches is turned on according to the control signal so as to adjust a voltage of the first control terminal for regulating a waveform of the output voltage.