Abstract: The present invention relates to a process of a package-then-etch three-dimensional package structure electrically connected by plated copper pillars. The process comprises the following steps: taking a metal carrier; preplating a surface of the metal carrier with a copper layer; forming an outer metal pin by means of electroplating; performing plastic packaging with epoxy resin; forming a metal circuit layer by means of electroplating; forming a conductive metal pillar by means of electroplating; surface-mounting a chip; performing plastic packaging; surface-mounting a passive device; performing plastic packaging; etching and windowing the carrier; forming an anti-oxidant metal layer by means of electroplating; and performing cutting to obtain a finished product. The integration level and the reliability can be improved.

Abstract: The present invention provides a packaging method and a packaging device for selectively encapsulating a packaging structure. The method includes: providing a substrate; mounting components on the substrate, the components including a component that needs to be encapsulated and a component that does not need to be encapsulated; forming a protective structure in an area of the component that does not need to be encapsulated so as to form a protective area for isolating the component that does not need to be encapsulated and an encapsulating area located outside the protective area; filling the encapsulating area with an injection molding material; and removing the protective structure. According to the present invention, any part of the packaging structure may be selectively encapsulated by self-adjustment as required. The operation is simple, and the process flow is simplified.

Abstract: The present invention relates to a process of a package-then-etch three-dimensional package structure electrically connected by plated copper pillars. The process comprises the following steps: taking a metal carrier; preplating a surface of the metal carrier with a copper layer; forming an outer metal pin by means of electroplating; performing plastic packaging with epoxy resin; forming a metal circuit layer by means of electroplating; forming a conductive metal pillar by means of electroplating; surface-mounting a chip; performing plastic packaging; surface-mounting a passive device; performing plastic packaging; etching and windowing the carrier; forming an anti-oxidant metal layer by means of electroplating; and performing cutting to obtain a finished product. The integration level and the reliability can be improved.

Abstract: The present invention relates to a package-before-etch three-dimensional package structure electrically connected by plated copper pillars and a process thereof. The process comprises the following steps: taking a metal carrier; preplating a surface of the metal carrier with a copper layer; forming an outer metal pin by means of electroplating; performing plastic packaging with epoxy resin; forming a metal circuit layer by means of electroplating; forming a conductive metal pillar by means of electroplating; surface-mounting a chip; performing plastic packaging; surface-mounting a passive device; performing plastic packaging; etching and windowing the carrier; forming an anti-oxidant metal layer by means of electroplating; and performing cutting to obtain a finished product. The integration level and the reliability can be improved.

Abstract: The present invention relates to a process of a surface-mounting three-dimensional package structure electrically connected by a pre-packaged metal, comprising: taking a metal sheet; punching or etching the metal sheet; packaging a conductive metal-pillar frame; performing windowing and slotting; taking a substrate on which a chip is surface-mounted; fitting the conductive metal-pillar frame; performing packaging and grinding; surface-mounting a passive device; performing plastic packaging and ball-mounting; and performing cutting. The process of the present invention can improve the integration level and the reliability.

Abstract: The present invention relates to a package-before-etch three-dimensional package structure electrically connected by plated copper pillars and a process thereof. The process comprises the following steps: taking a metal carrier; preplating a surface of the metal carrier with a copper layer; forming an outer metal pin by means of electroplating; performing plastic packaging with epoxy resin; forming a metal circuit layer by means of electroplating; forming a conductive metal pillar by means of electroplating; surface-mounting a chip; performing plastic packaging; surface-mounting a passive device; performing plastic packaging; etching and windowing the carrier; forming an anti-oxidant metal layer by means of electroplating; and performing cutting to obtain a finished product. The integration level and the reliability can be improved.

Abstract: Provided is an etching-before-packaging horizontal chip three-dimensional system level metal circuit board structure comprising a metal substrate frame; the metal substrate frame is provided with base islands and pins therein; the front faces of the base islands are provided with chips; the front faces of the chips are connected to the front faces of the pins via metal wires; conductive posts are disposed on the front faces or back faces of the pins; the peripheral areas of the base islands, the areas between the base islands and the pins, the areas between the pins, the areas above the base islands and the pins, the areas below the base islands and the pins, and the exteriors of the chips, the metal wires and the conductive posts are all encapsulated with molding compound.

Abstract: A first-etched and later-packaged three-dimensional system-in-package normal chip stack package structure and a processing method for manufacturing the same are provided. The structure includes: a die pad (1); a lead (2); a chip (4) provided on a top surface of the die pad (1) by a conductive or non-conductive adhesive material (3); a metal wire (5) via which a top surface of the chip (4) is connected to a top surface of the lead (2); a conductive pillar (6) provided on the surface of the lead (2); and a molding material (7).

Abstract: Provided is an etching-before-packaging three-dimensional system-level metal circuit board structure inversely provided with a chip. The structure comprises a metal substrate frame, wherein a base island and pins are arranged in the metal substrate frame; a chip is inversely arranged on a front face of the base island and the pins; a conductive pillar is arranged on a front face of the pins; the region on the periphery of the base island, the region between the base island and the pins, the region between one pin and another, the region above the base island and the pins, the region below the base island and the pins, and the outside of the chip and the conductive pillar are all enveloped with a plastic packaging material.

Abstract: A method for manufacturing a lead frame structure for semiconductor packaging. The method includes providing a metal substrate having a top surface and a back surface, forming a first photoresist film on the top surface of the metal substrate, forming a top surface etching pattern in the first photoresist film using photolithography, forming a second photoresist film on the back surface of the metal substrate, forming a back surface etching pattern in the second photoresist film using photolithography, performing an etching process on the top surface and the back surface of the metal substrate, removing the first photoresist film and the second photoresist film, placing the etched metal substrate in a mold, encapsulating the etched metal substrate using the mold; and performing a plating process on the encapsulated metal substrate.

Abstract: A no-exposed-pad ball grid array (BGA) packaging structure includes a metal substrate, a first die coupled to a top surface of the metal substrate, and a plurality of outer leads formed on the metal substrate and extending to the proximity of the die. A metal layer that contains a plurality of inner leads corresponding to the plurality of outer leads and extending to the proximity of the die is formed on the metal substrate by a multi-layer electrical plating process such that a lead pitch of the plurality of inner leads is significantly reduced. Furthermore, the die and the plurality of inner leads are connected by metal wires, and a plurality of solder balls is attached to a back surface of the plurality of outer leads and a die pad. The die, the plurality of inner leads, and the metal wires are sealed with a molding compound.

Abstract: A quad flat no-lead (QFN) packaging structure. The QFN packaging structure includes a metal substrate, a first die coupled to a top surface of the metal substrate, and a plurality of I/O pads formed on the metal substrate, and extending to the proximity of the die. The no-exposed-pad QFN packaging structure also includes a first metal layer containing a plurality of inner leads corresponding to the plurality of I/O pads and extending to proximity of the die and is formed on the metal substrate by a multi-layer electrical plating process. Further, the no-exposed-pad QFN packaging structure includes metal wires connecting the die and the plurality of inner leads, and a second metal layer formed on a back surface of the plurality of I/O pads.

Abstract: A quad flat no-lead (QFN) packaging structure. The QFN packaging structure includes a metal substrate, a first outer die pad formed on the metal substrate, and a first die coupled to a top surface of the first outer die pad. The QFN packaging structure also includes a plurality of I/O pads formed on the metal substrate, and a first metal layer containing a plurality of inner leads corresponding to the plurality of I/O pads and extending to proximity of the die. The first metal layer is formed on the metal substrate by a multi-layer electrical plating process such that a lead pitch of the plurality of inner leads is significantly reduced. Further, the QFN packaging structure includes metal wires connecting die and the plurality of inner leads, and a second metal layer formed on a back surface of the plurality of I/O pads and the die pad.

Abstract: A barrel-plating quad flat no-lead (QFN) package structure and a method for manufacturing the same. The method includes: providing a metal substrate for a plurality of QFN components; forming a first photoresist film on a top surface of the substrate; forming a plating pattern in the first photoresist film; forming a first metal layer containing a plurality of inner leads; etching the substrate from the back surface of the substrate to form a plurality of I/O pads; filling sealant in the etched areas; attaching at least one die in a predetermined region on the top surface of the substrate; connecting the die and the inner leads using metal wires; sealing the die, the inner leads, and the metal wires with a molding compound; separating the resulting joint QFN components into individual QFN components; and forming a second metal layer on the back surface of the I/O pads.

Abstract: A barrel-plating quad flat no-lead (QFN) package structure and a method for manufacturing the same. The method includes: providing a metal substrate for a plurality of QFN components; forming a first photoresist film on a top surface of the substrate; forming a plating pattern in the first photoresist film; forming a first metal layer containing a plurality of inner leads; etching the substrate from the back surface of the substrate to form a plurality of I/O pads; filling sealant in the etched areas; attaching at least one die in a predetermined region on the top surface of the substrate; connecting the die and the inner leads using metal wires; sealing the die, the inner leads, and the metal wires with a molding compound; separating the resulting joint QFN components into individual QFN components; and forming a second metal layer on the back surface of the I/O pads.

Abstract: A quad flat no-lead (QFN) packaging structure. The QFN packaging structure includes a metal substrate, a first outer die pad formed on the metal substrate, and a first die coupled to a top surface of the first outer die pad. The QFN packaging structure also includes a plurality of I/O pads formed on the metal substrate, and a first metal layer containing a plurality of inner leads corresponding to the plurality of I/O pads and extending to proximity of the die. The first metal layer is formed on the metal substrate by a multi-layer electrical plating process such that a lead pitch of the plurality of inner leads is significantly reduced. Further, the QFN packaging structure includes metal wires connecting die and the plurality of inner leads, and a second metal layer formed on a back surface of the plurality of I/O pads and the die pad.

Abstract: A no-exposed-pad ball grid array (BGA) packaging structure includes a metal substrate, a first die coupled to a top surface of the metal substrate, and a plurality of outer leads formed on the metal substrate and extending to the proximity of the die. A metal layer that contains a plurality of inner leads corresponding to the plurality of outer leads and extending to the proximity of the die is formed on the metal substrate by a multi-layer electrical plating process such that a lead pitch of the plurality of inner leads is significantly reduced. Furthermore, the die and the plurality of inner leads are connected by metal wires, and a plurality of solder balls is attached to a back surface of the plurality of outer leads and a die pad. The die, the plurality of inner leads, and the metal wires are sealed with a molding compound.

Abstract: A quad flat no-lead (QFN) packaging structure. The QFN packaging structure includes a metal substrate, a first die coupled to a top surface of the metal substrate, and a plurality of I/O pads formed on the metal substrate, and extending to the proximity of the die. The no-exposed-pad QFN packaging structure also includes a first metal layer containing a plurality of inner leads corresponding to the plurality of I/O pads and extending to proximity of the die and is formed on the metal substrate by a multi-layer electrical plating process. Further, the no-exposed-pad QFN packaging structure includes metal wires connecting the die and the plurality of inner leads, and a second metal layer formed on a back surface of the plurality of I/O pads.

Abstract: A method for manufacturing a lead frame structure for semiconductor packaging. The method includes providing a metal substrate having a top surface and a back surface, forming a first photoresist film on the top surface of the metal substrate, forming a top surface etching pattern in the first photoresist film using photolithography, forming a second photoresist film on the back surface of the metal substrate, forming a back surface etching pattern in the second photoresist film using photolithography, performing an etching process on the top surface and the back surface of the metal substrate, removing the first photoresist film and the second photoresist film, placing the etched metal substrate in a mold, encapsulating the etched metal substrate using the mold; and performing a plating process on the encapsulated metal substrate.

Abstract: The invention discloses a novel package structure of integrate circuit or discrete device and packaging method, and includes the lead pins adjacent to the island; another metal layer formed at the bottom of the island; another metal layer formed at the bottom of lead pins; chip mounted on the island; wires bonded between the chip and the lead pins; the molded body encapsulating the top surface and side surface of the island and the lead pins, small protrusions of the island and the lead pins below the molded body; in the individual package, the number of the island can be one or more, lead pins can be arrayed at one side of the island, also can be arrayed at two sides or three sides of the island, one or two rows of lead pins can be located around the island. The invention provides strong welding, good quality, low cost, smooth production, wide applicability, flexible arrangement of the chips.