Patents Assigned to JIANGSU PANGU SEMICONDUCTOR TECHNOLOGY CO., LTD
  • Publication number: 20240332240
    Abstract: A panel-level package structure includes a bonding layer; and a first temporary carrier and a second temporary carrier oppositely disposed on both sides of the bonding layer. Both the first temporary carrier and the second temporary carrier are connected to the bonding layer, and at least one bonding cavity is jointly formed by the bonding layer, the first temporary carrier and the second temporary carrier, so that integral package with a relatively large area may be achieved, which further improves package efficiency, thus reducing a package cost. A package structure with a double-sided symmetrical design may make products evenly stressed, which not only effectively solves problems of warping in products, but also greatly improves preparing efficiency, thus reducing a cost.
    Type: Application
    Filed: June 14, 2024
    Publication date: October 3, 2024
    Applicant: JIANGSU PANGU SEMICONDUCTOR TECHNOLOGY CO., LTD
    Inventors: Zhiyi XIAO, Shuying MA, Jiao WANG