Abstract: A fabric interconnect system may provide a data path between nodes and/or processing elements within an interconnection fabric. Identifiers may be assigned to particular components associated with the interconnection fabric. These identifiers may uniquely identify the particular components, and may indicate a path between a root node and a particular component. In some embodiments, the identifiers include turn counts and turn values that specify a turn-based bath from the root node to a particular component. One or more identifier acceptance rules may be used in order to determine whether a given component should accept and store a particular identifier that the component receives. For example, a lower priority identifier may be discarded in favor of a higher priority identifier.

Abstract: The invention utilizes a separate queue per output port as implemented in the traditional simple queuing schemes of the prior art. Further, it also uses the information found in the packet header to determine the output port and the next output port. Based on this information, it utilizes queues dedicated to congested flows, or “Congested Flow” queues. When the switch determines that, based on the first output port and the second subsequent output port, a packet in the output queue is destined for a congested path, it sets the offending packet aside in a Congested Flow queue, thereby allowing other packets destined for the first output port to continue to be transmitted. In this way, the HOL blocking issue is addressed, without the need for a significantly increased number of output queues.

Abstract: A method and structure(s) for providing a data path between and among nodes and processing elements within an interconnection fabric are described. More specifically, a device comprising a first circuit configured to couple between a first bus and a link is described. The circuit may be configured to operate as a bridge, support PCI configuration cycles, send outgoing information serially through the link in a format different from that of the first bus, and allow a host processor, communicating through the first bus, to selectively address one or more remote devices to which the device is configured to allow access. In some embodiments, the first circuit may support “spoof-proof” data protocols, and the device may operate in multiple modes including root bridge, leaf bridge, and gateway mode. Multiple addressing models may also be used.

Abstract: A method and structure(s) for providing a data path between and among nodes and processing elements within an interconnection fabric are described. More specifically, a device comprising a first circuit configured to couple between a first bus and a link is described. The circuit may be configured to operate as a bridge, support PCI configuration cycles, send outgoing information serially through the link in a format different from that of the first bus, and allow a host processor, communicating through the first bus, to selectively address one or more remote devices to which the device is configured to allow access. In some embodiments, the first circuit may support “spoof-proof” data protocols, and the device may operate in multiple modes including root bridge, leaf bridge, and gateway mode. Multiple addressing models may also be used.

Abstract: The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric.

Abstract: The invention provides a system and method for identifying and communicating congested paths throughout a network fabric. Briefly, the present invention augments the congestion management mechanism defined in ASI to allow for the communication of congested paths through the fabric, rather than the simple congested output port notification supported today through the use of DLLPs. Further, it also uses the communication mechanisms already defined in the ASI specification to implement this additional capability. Specifically, the present invention uses Transaction Layer Packets (TLPs) to communicate the information concerning congested flows throughout the network. This packet type allows the inclusion of much more information than DLLPs, allowing a more comprehensive and elegant solution to the issue of congestion management in an Advanced Switching network fabric.

Abstract: An improved architecture for switches and a method for transmitting data with the switching are disclosed. An increased amount of memory is utilized, operating at speeds lower than are required by Input Queued switches, and a simple scheduling algorithm. The architecture divides the input ports into groups, where each input port group has an associated set of memory elements. Incoming packets are routed to the appropriate element in the set of memory elements. The number of groups and the number of ports that are included in each group can be varied, allowing the architecture to be modified based on the system architecture, the semiconductor technology, and other design considerations.

Abstract: The invention provides an improved architecture for credit based flow control. Briefly, the memory space within the receiving switch is separated into two parts, a statically allocated portion and a dynamically allocated portion. Packets are first placed in the dynamically allocated portion, and the credits are returned immediately. When the dynamically allocated portion has no additional space, the packets are then stored in the memory portion statically allocated to the specific virtual circuit. Credits are returned when the packets are removed from the statically allocated memory portion. This scenario allows the immediate return of credits when there is space available in the dynamically allocated memory portion. It also allows improved sharing of the overall memory since more of the overall memory can be made available to a particular virtual circuit.

Abstract: The present invention provides an improved architecture and method for the processing and transmission of multicast packets within a switching device. Briefly, as multicast packets arrive, a copy of the packet, or preferably a pointer for it, is placed in a multicast FIFO. As each pointer reaches the head of the FIFO, the destination output ports via which the packet is to be transmitted are determined, based on the packet's multicast group identifier (MGID). In the preferred embodiment, there is a dedicated multicast output queue associated with each output port. Copies of the packet, or preferably pointers to the packet, are then stored in those output queues associated with the specified destination output ports. In this way, a congested output port only affects the transmission of multicast packets via that congested port.

Abstract: The present invention provides a system and method for encapsulating protocols across a switching fabric network. Packets, which may utilize any underlying protocol, are encapsulated with a route header. This route header contains path routing, traffic and packet size information. A novel path routing scheme is used to route packets across the fabric, where the fabric has a plurality of switches, each having a plurality of ports. Each switch uses only data from within the packet and its own port count to determine the appropriate output port. There is no need to node or address lookup mechanisms in the switches.

Abstract: The invention provides an improved architecture for credit based flow control. Briefly, the memory space within the receiving switch is separated into two parts, a statically allocated portion and a dynamically allocated portion. Packets are first placed in the dynamically allocated portion, and the credits are returned immediately. When the dynamically allocated portion has no additional space, the packets are then stored in the memory portion statically allocated to the specific virtual circuit. Credits are returned when the packets are removed from the statically allocated memory portion. This scenario allows the immediate return of credits when there is space available in the dynamically allocated memory portion. It also allows improved sharing of the overall memory since more of the overall memory can be made available to a particular virtual circuit.

Abstract: The present invention provides an improved apparatus and method for the receipt of high-speed sequential data streams. It utilizes the concept of banked memories to reduce the required speed and size of the input buffers used to receive the data streams. This allows the device to employ large, relatively slow memory elements, thereby permitting large amounts of sequential data to be stored by the receiving device. Using control information that was written as the data was being stored in the memory banks, a reordering element is later able to retrieve the data elements from the plurality of memory banks, in an order that is different from that in which the stream was received, and to reassemble the data stream into the original sequence.