Abstract: A method for operating a multi-tasking, interrupt capable microprocessor under inverse processor state usage is provided whereby the effective time for both interrupt processing and switching context between task execution and interrupt processing is reduced, thereby significantly enhancing the overall performance of the operating system kernel. This increased performance is achieved by the elimination of the previously needed temporary storage in memory of volatile global registers and task context data. Volatile global registers are preserved in local registers during interrupt processing, thereby eliminating time-consuming transfers of data to and from temporary memory storage locations. A task procedure stack, rather than the interrupt stack, is utilized for interrupt records and frames containing user task context data. This is accomplished by programmably creating an inverse processor state designation.