Abstract: A method for enhancing speed of incremental backup, a bridge device, and a storage system are provided. The method includes: regarding a predetermined location within the storage system, determining whether a record file exists; in response to the record file existing, determining whether any file needing to be compared exists; in response to said any file needing to be compared existing, comparing said any file needing to be compared with content of the record file to generate at least one comparison result, wherein said at least one comparison result indicates whether a set of attributes of said any file needing to be compared completely exist in the record file; according to said at least one comparison result, determining whether any difference is found; and in response to said any difference being not found, preventing triggering any backup from a source storage device to a target storage device.

Abstract: The present invention provides a data protection method and storage device. The data protection method includes: (A): during an initial period after the storage device is connected to a host, detecting the storage device and determining whether the storage device needs to be performed with data protection; (B): when the storage device needs to be performed with data protection in Step (A), modifying a predetermined writing destination that the host writes data to a storage unit of the storage device, to make the data from the host be written to another writing destination rather than being written to said writing destination; or writing the data from the host into a control chip or a bridge chip of an inner memory or an inner register, rather than writing the data from the host into the storage device; and (C): reporting to the host that the writing operation is completed.

Abstract: A transmission interface circuit includes a power supply port, a first power path, first data transmission path, second power path and controller. The first power port is coupled to the storage device to provide the storage device with power. The first data transmission path is coupled between the storage device and the electronic device to perform data transmission between the storage device and the electronic device. The second power port is coupled to the electronic device to provide the electronic device with power. The controller respectively control enables or disables the first power path, the second power path and the first data transmission path according to the information transmitted from the electronic device.

Abstract: The present invention provides a memory size determining method which includes: writing a magic string into an initial location of the memory space of a memory; performing a first time reading with a first range on the memory, and if the magic string is not found in the first time reading, performing a second time reading with a second range on the memory, until the magic string is found; and if the magic string is found in the N-th time reading, determining the N-th range corresponding to the N-th time reading as the memory size, wherein N is an positive integer larger than or equal to 1.

Abstract: An exemplary method of error checking and correction applied in a multi-channel system, includes: performing error checking and correction encoding upon a first data packet of a first channel and a second data packet of a second channel, and generating a first horizontal error correction code and a second horizontal error correction code; performing error checking and correction encoding upon a first mixed data packet and a second mixed data packet, and generating a first vertical error correction code and a second vertical error correction code; and combining the first data packet, the first horizontal error correction code and the first vertical error correction code into the first encoded data packet of the first channel, and combining the second data packet, the second horizontal error correction code and the second vertical error correction code into the second encoded data packet of the second channel.

Abstract: A method of signal identification, including: receiving a signal; utilizing a clock generated by a ring oscillator to sample the signal continuously to generate a plurality of sampled signals; counting each sampled signal length corresponding to successive sampled signals each having an identical value; and identifying a content of the signal according to a plurality of sampled signal lengths. A signal identification apparatus, including: a receiving circuit, arranged for receiving a signal; a ring oscillator, arranged for generating a clock; a sampling circuit, arranged for sampling the signal continuously to generate a plurality of sampled signal; a counter, arranged for counting each sampled signal length corresponding to successive sampled signals each having an identical value; and a determining unit, arranged for identifying a content of the signal according to a plurality of sampled signal lengths.

Abstract: An exemplary method of error checking and correction applied in a multi-channel system, includes: performing error checking and correction encoding upon a first data packet of a first channel and a second data packet of a second channel, and generating a first horizontal error correction code and a second horizontal error correction code; performing error checking and correction encoding upon a first mixed data packet and a second mixed data packet, and generating a first vertical error correction code and a second vertical error correction code; and combining the first data packet, the first horizontal error correction code and the first vertical error correction code into the first encoded data packet of the first channel, and combining the second data packet, the second horizontal error correction code and the second vertical error correction code into the second encoded data packet of the second channel.

Abstract: A method of error checking and correction includes: performing compression upon an original data packet and generating a compressed data packet; determining an error correcting code length according to a data length; generating an error correcting code by performing error checking and correction encoding upon a packet data according to the error correcting code length; and combining the packet data and error correcting code into an encoded data packet. A method of error checking and correction includes: reading an encoded data packet, wherein the encoded data packet includes a packet data and an error correcting code, and the packet data includes a compressed data packet; generating a decoded compressed data packet corresponding to the compressed data packet by performing error checking and correction decoding upon the packet data according to the error correcting code; and performing decompression upon the decoded compressed data packet to generate a decompressed data packet.

Abstract: A USB device with a clock calibration function and a method for calibrating reference clocks of a USB device are provided. A USB 2.0 initial calibration is performed on the USB device in order to control an embedded oscillator (EMOSC) of the USB device to output a first reference clock compliance USB 2.0 specification and USB 3.0 specification during the initialization phase. After that, a USB 3.0 on-line calibration is performed on the USB device in order to control the EMOSC of the USB device to calibrate a second reference clock during a super-speed mode of USB 3.0 specification.

Abstract: A memory control method, including: writing a write-in data which has a logical address into a write-in cache buffer; generating a write-in address mapping table which maps the logical address of the data to a physical address of a main memory, and writing the write-in address mapping table into a cached data mapping table write buffer; writing the write-in data into the main memory according to the write-in address mapping table; and when an available storage space of the cached data mapping table write buffer is reduced to reach a predetermined threshold, writing the address mapping table in the cached data mapping table write buffer into the main memory, and storing a corresponding main memory write-in address mapping table into a global mapping table buffer.

Abstract: The present invention provides an electronic system with power saving function. In a first embodiment, the electronic system comprises a processing unit and a storage device. The storage device has a transmission interface, and the storage device is coupled to the processing unit via the transmission interface, wherein when the electronic system enters into a hibernate mode, the processing unit will turn off power supply of the storage device completely via the transmission interface. In a second embodiment, the electronic system comprises a processing unit and a storage device. The storage device has a transmission interface and an independent signal pin, and the storage device is coupled to the processing unit via the transmission interface and the independent signal pin, wherein when the electronic system enters into a hibernate mode, the processing unit will turn off power supply of the storage device completely via the independent signal pin.

Abstract: The present invention provides a method for estimating a capacity usage status of a storage unit, where the storage unit includes a plurality of sectors. The method includes: estimating capacity usage statuses of a portion of sectors; and utilizing a controller to estimate the capacity usage status of the storage unit according to the estimated capacity usage statuses of the portion of sectors in a situation of not estimating capacity usage statuses of all of the sectors of the storage unit.

Abstract: A time aligning circuit includes a plurality of buffers, a plurality of delay selectors, a plurality of adjustment symbol generators, and a controller. Each buffer receives an ordered set on a corresponding lane. Each delay selector delays an output of the ordered set of the corresponding buffer. Each adjustment symbol generator outputs an adjustment symbol or the output received from the corresponding delay selector according to an adjustment control signal. When an initial symbol of a designated delay selector is detected but initial symbols of other delay selectors are not received yet, the controller generates the delay control signal to the designated delay selector and generates the adjustment control signal to control a designated adjustment symbol generator corresponding to the designated delay selector in order to output one adjustment symbol until initial signals of all delay selectors are detected.

Abstract: By taking advantage of parallel data processing and transmission techniques, the data access rate of a redundant array of independent disks (RAID) level 5 can be boosted significantly. A data distribution and aggregation unit is utilized to distribute a data stream into a plurality of data sub-streams based on the primitive data access block of storage devices as a processing unit of data writing, or to aggregate a plurality of data sub-streams to form a data stream based on the primitive data access block of storage devices as a processing unit of data reading. An exclusive OR operation unit capable of parallel data processing is introduced for performing data processing on the plurality of data sub-streams simultaneously. The data transmission of each data sub-stream is controlled individually by one of a plurality of transmission controllers.

Abstract: A method of network packet receiving management includes: providing a buffer unit which includes a plurality of data blocks with a first packet number and a plurality of data blocks with a second number of packets, wherein the data blocks with the first packet number are for storing a plurality of first network packets according to a first array data structure, respectively, the first array data structure has a plurality of first packet descriptors corresponding to the first packet number, and the data blocks with the second number of packets do not correspond to any packet descriptor; and when a first data block corresponding to a first packet descriptor successively receives a first network packet, changing the first packet descriptor corresponding to the first data block to indicate a second data block which does not correspond to any packet descriptor.

Abstract: An allocating method for a flash memory is disclosed. The allocating method includes the following steps: adjusting a preliminary data storage capacity corresponding to the flash memory for determining a real data storage capacity of the flash memory; adjusting a preliminary spare area capacity corresponding to the flash memory for determining a real spare area capacity of the flash memory, wherein a total capacity of the preliminary data storage capacity and the preliminary spare area capacity is equal to the total capacity of the real data storage capacity and the real spare area capacity; and allocating the real data storage capacity and the real spare area capacity to the flash memory, wherein the real data storage capacity stores data, and the real spare area capacity stores parity codes generated by an error codes correction algorithm performed upon the stored data in the real data storage capacity.

Abstract: A card reader with power-saving function is used for being inserted with a memory card so that a computer can access the memory card through the card reader. When the memory card is inserted in the card reader, the card reader is enabled to operate. On the other hand, when the memory card is not inserted in the card reader, the card reader enters to a power-down mode for saving power.

Abstract: When booting a host, a host peripheral system sends a boot code to the host for controlling the booting operation of the host via a serial transmission line, and loads an external program code into the host. After setting up a transmission mechanism through executing the external program code, the host can forward a write command to the host peripheral system for writing the data provided by the external program code to the command identification sector of the non-volatile memory of the host peripheral system, and the host peripheral system is capable of identifying the data as a command and executes functional operations corresponding to the command. After finishing the functional operations, the host peripheral system forwards a finish signal to the host, and the host is able to send a read command for fetching the data signal generated in the functional operations.

Abstract: A three-dimensional capacitor structure has a first conductive layer, a second conductive layer disposed above the first conductive layer, and a plug layer disposed therebetween. The first conductive layer includes a plurality of grid units arranged in a matrix, where in odd rows of the matrix, a first conductive grid is located in each odd column, and a first circular hole is located in each even column. Additionally, a first conductive island is located within each first circular hole. The pattern of the second conductive grids, the second circular holes, and the second conductive island of the second conductive layer is mismatched with that of the first conductive layer. The plug layer has a plurality of plugs disposed in between each first conductive island and each second conductive grid, and in between each first conductive grid and each second conductive island.

Abstract: An impedance matching circuit includes a plurality of latch circuits, each connected to one of a plurality of logic circuits. Each latch circuit has a first input commonly connected to a signal line and a second input connected to one of a plurality of non-overlapping digital clock signals. Approximately half of the maximum output resistance is compared with an external resistor and the result latched by a latch circuit corresponding to the most significant bit of the control signal, effectively halving the possible voltage range. A next latch circuit latches the second most significant bit of the control signal similarly, and a third latch circuit latches the remaining bit of the control signal. The control signal controls a binary weighted transistor array that adjusts input voltage. An output signal goes to an output register where it is used to control an output driver.