Patents Assigned to JMJ KOREA CO., LTD.
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Publication number: 20250018498Abstract: Provided is an ultrasonic welding system and a power module package for a power converting apparatus to which a substrate where connection members are ultrasonic welded by using the system is applied, wherein the ultrasonic welding system includes a waffle pack 110 on which connection members 10 to be ultrasonic welded onto a substrate 20 are arranged in a specific form, a centering aligning unit 120 which aligns and centers the connection members 10 transferred from the waffle pack 110, an ultrasonic welding part 130 which fixes the substrate 20 and ultrasonic welds the connection members 10 aligned by the centering aligning unit 120 onto the substrate 20, and a picker 140 which separately picks the connection members 10 from the waffle pack 110 to be transferred to the centering aligning unit 120 and re-picks the aligned connection members 10 from the centering aligning unit 120 to be transferred to ultrasonic welding positions on the substrate 20 fixed to the ultrasonic welding part 130, wherein the connecType: ApplicationFiled: February 14, 2024Publication date: January 16, 2025Applicant: JMJ Korea Co., Ltd.Inventors: Yun Hwa CHOI, Jung Min PARK
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Patent number: 12170260Abstract: Provided is a semiconductor package including: a pad substrate on which a semiconductor chip is installed; a solder formed on the pad substrate having a length same as or longer than a side of the semiconductor chip; and an intagliated groove formed on the pad substrate having a length longer than at least the side of the semiconductor chip and filled with at least a certain amount of melted solder, wherein the solder having a thickness of at least 1 ?m or above is filled in the intagliated groove to have a length of at least 3 ?m or above and an intermetallic compound layer is formed on a certain area included in an inner wall of the intagliated groove. Accordingly, movement of the semiconductor chip may be restricted so that the quality of following processes may be improved, and electrical and mechanical combination between the solder and the pad substrate may be stabled.Type: GrantFiled: December 6, 2021Date of Patent: December 17, 2024Assignee: JMJ Korea Co., Ltd.Inventor: Yun Hwa Choi
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Publication number: 20240395761Abstract: The present invention relates to a metal clip structure and a semiconductor package including the same, and more particularly, to a metal clip structure and a semiconductor package including the same which may be light-weighted, increase bond strength of a conductive wire, and minimize contamination occurring due to a solder material used to bond a semiconductor chip to a metal pad.Type: ApplicationFiled: January 29, 2024Publication date: November 28, 2024Applicant: JMJ Korea Co., Ltd.Inventor: Yun Hwa CHOI
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Publication number: 20240379612Abstract: The present invention relates to an apparatus for bonding clips, a method of bonding clips, and a semiconductor package including semiconductor chips to which the clips are bonded using the method, and more particularly, to an apparatus for bonding clips, a method of bonding clips, and a semiconductor package including semiconductor chips to which the clips are bonded using the method, wherein the clips are sequentially bonded to the semiconductor chips by 1 unit so that a pitch difference between a lead frame array and a clip array is separately corrected to be the same and thereby, misalignment may be minimized so as to increase bonding accuracy of the clips to the semiconductor chips.Type: ApplicationFiled: March 26, 2024Publication date: November 14, 2024Applicant: JMJ Korea Co., Ltd.Inventors: Yun Hwa CHOI, Ji Won CHOI
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Publication number: 20240355723Abstract: The present invention provides a semiconductor package including a lead frame pad 110 including at least one first substrate 111 and at least one second substrate 112 structurally bonded to one surface of the first substrate 111, at least one semiconductor chip 120 bonded onto the second substrate 112 by using a conductive adhesive, a lead frame lead 130 including at least one first terminal 131 structurally or electrically connected to the lead frame pad 110 and at least one second terminal 132 spaced apart from the lead frame pad 110 by a regular distance, an electrical connection member 140 electrically connecting the semiconductor chip 120 with the second terminal 132, and a housing 150 partially or entirely covering the semiconductor chip 120 and the lead frame pad 110. Here, the lead frame lead 130 is exposed and extended to the outside of the housing 150 and the thickness of the second substrate 112 is less than the thickness of the first substrate 111.Type: ApplicationFiled: December 27, 2023Publication date: October 24, 2024Applicant: JMJ Korea Co., Ltd.Inventor: Yun Hwa CHOI
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Publication number: 20240297096Abstract: The present invention relates to a semiconductor package having a heat emitting post bonded thereto and a method of manufacturing the same, and more particularly, to a semiconductor package having a heat emitting post bonded thereto and a method of manufacturing the same that may increase bond strength of the heat emitting post and improve durability of bonding members contacting cooling water.Type: ApplicationFiled: August 29, 2023Publication date: September 5, 2024Applicant: JMJ Korea Co., Ltd.Inventor: Yun Hwa CHOI
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Publication number: 20240290700Abstract: Provided is a bonding substrate, a semiconductor package having a double-sided substrate, a method of manufacturing the bonding substrate, and a method of manufacturing the semiconductor package having a double-sided substrate, wherein the bonding substrate includes at least one upper substrate; at least one lower substrate which faces and is spaced apart from the upper substrate by a regular distance; and connecting members which comprises at least two layers formed of each different metal and is structurally or electrically ultrasonic bonded to the upper substrate or the lower substrate by using an ultrasonic bonding device. Accordingly, a tolerance for a vertically separated distance between upper and lower substrates may be minimized through ultrasonic bonding between the substrate and the connecting member and structural stress generated while molding may be reduced by using connecting members having each different Coefficient of Thermal Expansion (CTE).Type: ApplicationFiled: November 22, 2023Publication date: August 29, 2024Applicant: JMJ Korea Co., Ltd.Inventor: Yun Hwa CHOI
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Publication number: 20240250057Abstract: Provided is a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package and a method of manufacturing the same in which stress applied while molding is efficiently dispersed by a three-dimensional clip structure so that structural reliability may be improved.Type: ApplicationFiled: October 27, 2023Publication date: July 25, 2024Applicant: JMJ Korea Co., Ltd.Inventor: Yun Hwa CHOI
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Publication number: 20240234288Abstract: Provided is a semiconductor package, and more particularly, a semiconductor package in which a semiconductor device is protected in such a way that stress from push and thermal expansion generated while molding by a package housing is dispersed or absorbed through an electrical connecting member having a non-vertical structure bent in a z-letter shape.Type: ApplicationFiled: October 27, 2023Publication date: July 11, 2024Applicant: JMJ Korea Co., Ltd.Inventor: Yun Hwa CHOI
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Patent number: 12027445Abstract: Provided is a system for cooling semiconductor components including: a cover body including at least one upper cover and lower cover, which are separated from each other, face each other, and are combined to form a coolant flow path in an inner space thereof; an inlet combined to one side of the cover body and used for a coolant to flow in; an outlet combined to the other side of the cover body and used for the coolant to be discharged; at least one connecting part pin inserted and arranged toward a flowing direction of the coolant in the inner space of the cover body; and insertion grooves formed for the connecting part pins to be inserted in the inner space of the cover body, wherein the upper cover or the lower cover of the cover body is combined to at least one of the upper surfaces or the lower surfaces of semiconductor components by using connecting members so that heat transmitted from the semiconductor components to the connecting part pins is efficiently radiated by enlarging an area contacting the cType: GrantFiled: November 4, 2021Date of Patent: July 2, 2024Assignee: JMJ Korea Co., Ltd.Inventor: Yun Hwa Choi
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Publication number: 20240178094Abstract: Provided is a semiconductor package in which a heat radiation substrate and a housing are separately formed and are bonded to each other through an insulating layer or an adhesive member so that a manufacturing process thereof is suitable for mass-production and thereby, productivity may be increased.Type: ApplicationFiled: May 7, 2023Publication date: May 30, 2024Applicant: JMJ Korea Co., Ltd.Inventor: Yun Hwa CHOI
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Patent number: 11908824Abstract: The present invention relates to a semiconductor package in which a metal bridge, which is bent and has elasticity and a non-vertical structure, may protect a semiconductor chip in such a way that push-stress occurring while molding is relieved by being absorbed or dispersed by being diverted, a method of manufacturing the same, and the metal bridge applied to the semiconductor package.Type: GrantFiled: January 3, 2022Date of Patent: February 20, 2024Assignee: JMJ Korea Co., Ltd.Inventor: Yun Hwa Choi
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Patent number: 11908766Abstract: The present invention relates to a cooling system where a semiconductor component including a semiconductor chip and a cooling apparatus are joined, wherein a coolant is supplied to a substrate, on which a semiconductor chip is installed, through an opening member of the cooling apparatus so that a surface of the substrate may be directly cooled by the coolant so as to improve cooling efficiency, and a cooling post structure, which enables the coolant to smoothly flow, is used to further improve cooling efficiency.Type: GrantFiled: September 28, 2021Date of Patent: February 20, 2024Assignee: JMJ Korea Co., Ltd.Inventor: Yun Hwa Choi
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Patent number: 11823920Abstract: Provided is an apparatus for attaching semiconductor parts. The apparatus includes a substrate loading unit, at least one semiconductor part loader, a first vision examination unit, at least one semiconductor part picker, at least one adhesive hardening unit, and a substrate unloading unit, wherein the substrate loading unit supplies a substrate on which semiconductor units are arranged, the at least one semiconductor part loader supplies semiconductor parts, the first vision examination unit examines arrangement states of the semiconductor units, the at least one semiconductor part picker mounts semiconductor parts in the semiconductor units, the at least one adhesive hardening unit hardens and attaches adhesives interposed between the semiconductor units and the semiconductor parts, and the substrate unloading unit releases the substrate on which semiconductor parts are mounted.Type: GrantFiled: December 16, 2020Date of Patent: November 21, 2023Assignee: JMJ Korea Co., Ltd.Inventors: Yun Hwa Choi, Jung Min Park
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Patent number: 11798864Abstract: Provided is a semiconductor package including: a first substrate comprising a specific pattern formed thereon to enable electrical connection; a second substrate, which is spaced apart from and faces the first substrate, comprising a specific pattern formed thereon to enable electrical connection; at least one semiconductor chip attached to the first substrate; at least one metal post formed in a non-vertical structure between the first substrate and the second substrate for dispersing a coefficient of thermal expansion (CTE) stress directly generated from the second substrate, wherein the metal post comprises one end attached on the at least one semiconductor chip, and the other end attached on the pattern of the first substrate or the second substrate; at least one terminal lead electrically connected to the first substrate or the second substrate; and a package housing covering the first and second substrates and exposing the terminal leads to the outside.Type: GrantFiled: January 13, 2021Date of Patent: October 24, 2023Assignee: JMJ Korea Co., Ltd.Inventor: Yun Hwa Choi
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Publication number: 20230326830Abstract: Provided is a semiconductor package module including vertical terminals in which the vertical terminals are connected to increase the number of terminals, problems on bending of the terminals may be solved while in electrical connection, and resistance of electrical signals may be reduced.Type: ApplicationFiled: February 13, 2023Publication date: October 12, 2023Applicant: JMJ Korea Co., Ltd.Inventor: Yun Hwa CHOI
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Publication number: 20230282566Abstract: The present invention relates to a semiconductor package having a negative patterned substrate and a method of manufacturing the same, and more particularly, to a semiconductor package having a negative patterned substrate and a method of manufacturing the same, wherein in the semiconductor package and the method of manufacturing the same, a molding resin may not flow to the outside of the negative patterned substrate so as to prevent the substrate from being contaminated and a negative space is filled with the molding resin so as to stably perform a molding process.Type: ApplicationFiled: December 5, 2022Publication date: September 7, 2023Applicant: JMJ Korea Co., Ltd.Inventor: Yun Hwa CHOI
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Publication number: 20230268252Abstract: Provided is a semiconductor package including a heat radiation structure, a cooling system applying the semiconductor package, a substrate including a heat radiation structure, and a method of manufacturing the substrate, and more particularly, a semiconductor package including a heat radiation structure, a cooling system applying the semiconductor package, a substrate including a heat radiation structure, and a method of manufacturing the substrate, in which an area contacting a coolant enlarges through heat radiating posts having various forms and structures and a coolant flow path is formed by post holes so that heat generated from semiconductor chips may be efficiently cooled.Type: ApplicationFiled: October 12, 2022Publication date: August 24, 2023Applicant: JMJ Korea Co., Ltd.Inventor: Yun Hwa CHOI
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Patent number: 11721615Abstract: Provided is a coupled semiconductor package including at least two substrate pads; at least one semiconductor chip installed on each of the substrate pads; at least one terminal each of which is electrically connected to each substrate pad and each semiconductor chip; and a package housing covering a part of the at least one semiconductor chip and the at least one terminal, wherein lower surfaces of one or more substrate pads are formed to be electrically connected and lower surfaces of another one or more substrate pads are formed to be electrically insulated. Accordingly, partial insulation may be economically realized without applying an insulating material to a heat sink, when the package is joined to the heat sink.Type: GrantFiled: April 11, 2021Date of Patent: August 8, 2023Assignee: JMJ Korea Co., Ltd.Inventor: Yun Hwa Choi
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Patent number: D1049065Type: GrantFiled: July 12, 2021Date of Patent: October 29, 2024Assignee: JMJ KOREA CO., LTD.Inventor: Yun Hwa Choi