Patents Assigned to John Caywood
  • Low voltage single supply CMOS electrically erasable read-only memory
    Patent number: 5790455
    Abstract: P channel EEPROM cells are designed for integration into arrays written with single polarity signals developed from small, low power charge pumps. These cells reduce the additional masking steps that must be added to a CMOS logic process for EEPROM to only one additional step. The novel cells of this invention enable the array to function with a V.sub.PP about 2 V less than that required by an N channel EEPROM cell, with similar writing speed and tunnel oxide thickness.
    Type: Grant
    Filed: January 2, 1997
    Date of Patent: August 4, 1998
    Assignee: John Caywood
    Inventor: John M. Caywood
  • Flash EPROM cell and method for operating same
    Patent number: 5235544
    Abstract: A flash EPROM cell may be erased by placing a negative voltage on the control gate of a flash EPROM cell having spaced apart source and drain regions in a semiconductor substrate, and having a floating gate, a control gate and a sidewall gate, while biasing the drain at a positive voltage.
    Type: Grant
    Filed: November 9, 1990
    Date of Patent: August 10, 1993
    Assignee: John Caywood
    Inventor: John Caywood