Abstract: The present invention is directed to fabricating a MOSFET-controlled FEA, in which the emitter array and the cathode electrode are separated and connected to each other by a MOSFET, the cathode electrode and the n-well beneath the emitter array thereby being used as a source and a drain of the MOSFET.

Abstract: A method for preparing spherical phosphor particles is disclosed, wherein a precursor solution of phosphors is decomposed to solid particles by aerosol pyrolysis and rapid cooling and subsequently the solid particles are heat-treated at a temperature of 1000.degree. C. to 1600.degree. C. for a period of 1 hour to 9 hours.

Abstract: The present invention provides field emitter arrays (FEAs) having incorporated with metal oxide semiconductor field effect transistors (MOSFETs) and method for fabricating the same which realizes a simultaneous fabrication of two kinds of devices, namely, the FEA and MOSFETs, by using common processing steps among the processes of fabricating the Si-FEA or the metal FEA and the MOSFETs, wherein the method comprises steps of forming field emission tips and active regions for MOSFETs by oxidizing selected portions of the silicon nitride layer, forming a gate insulating oxide layers for the FEA and field oxide layers for MOSFETs simultaneously by the LOCOS method and connecting gate electrodes(row line) and cathode electrodes(column line) of the FEA to MOSFETs.

Abstract: The present invention privides a method for manufacturing an ISRC MOSFET, comprising steps of forming an isolating layer through the LOCOS process, depositing a mask oxide layer, exposing only the part of silicon substrate for forming the channel and shallow junction of source/drain layers, depositing the first nitride layer over the resultant substrate, dry-etching the first nitride layer to form a nitride side-wall, forming an oxide layer being recessed into the channel, wet-etching the nitride side-wall, forming two doped layers for the shallow source/drain by an N.sup.+ or P.sup.+ ion-implantation, depositing the second nitride layer, dry-etching for forming a nitride side-wall, forming a P.sup.- or N.sup.- doped layer between the two doped layers, forming a gate oxide layer on the P.sup.- or N.sup.

Abstract: The present invention provides field emitter arrays (FEAs) incorporated with metal oxide semiconductor field effect transistors (MOSFETs) and method for fabricating the same which realizes a simultaneous fabrication of two kinds of devices, namely, an FEA and MOSFETs, by using common processing steps among the processes of fabricating Si-FEAs or metal FEAs and MOSFETs, wherein the method comprises steps of forming field emission tips and active regions for MOSFETs by oxidizing selected portions of a silicon nitride layer, forming a gate insulating oxide layer for the FEA and field oxide layers for MOSFETs simultaneously by the LOGOS method and connecting gate electrodes (row line) and cathode electrodes (column line) of the FEA to MOSFETs.

Abstract: The present invention provides a method for manufacturing field emitter arrays, comprising steps of forming a n.sup.+ -layer in a polycrystalline or amorphous silicon layer deposited on an insulating substrate, making an oxide layer disk pattern on said silicon layer, etching said silicon layer isotropically, forming a silicon oxide layer on the upper part of said silicon layer by means of the first oxidation, which results in field emitter tips, making hollows, depositing a silicon nitride layer with a predetermined thickness on said silicon oxide layer, removing said silicon nitride layer except that of the side-wall parts around said field emitter tips, forming a gate insulating layer by means of the second oxidation, removing said silicon nitride layer of said sidewall parts around said tips, making contact window, and forming gate electrodes and cathode contacts by depositing gate metal on said gate insulating layers.

Abstract: The present invention provides a method for manufacturing a low voltage driven field emitter array, comprising steps of forming a thin buffer layer on a silicon substrate, making a pattern with lots of silicon nitride masks on the layer, oxidizing the upper part of the substrate and forming a relatively thick oxide layer onto the substrate except the part under the nitride masks, during which the thick oxide layer upheaves the edges of the nitride masks and extends inwardly under the nitride masks so that the edges of the thick oxide layer under the nitride masks may have a kind of bird's beak shape in cross section, etching away the nitride mask pattern, exposing the silicon substrate for the circular parts surrounded by the bird's beak shape edges by etching away the thin buffer layer, etching away the exposed substrate for making gate holes of undercut shape, and forming metal layers on the substrate and the bottom of the gate holes by evaporating a matalic evaporant downwardly and vertically against the s