Abstract: A trench gate silicon carbide metal oxide semiconductor field effect transistor (MOSFET) device and a fabrication method thereof. A second conductive heavily doped layer at the bottom corner of a trench gate is electrically connected to a second conductive heavily doped layer on another side edge of the trench gate through a layout design, which ensures a ground potential during voltage blocking state. This design protects the insulating layer in the trench gate and the Schottky contact in a junction barrier Schottky (JBS) diode, thereby enhancing device reliability. Moreover, in a diode operating mode, P+ on the left and right sides of the trench gate are connected to a positive potential. When the P+/N? junction is activated, the conductivity modulation can be implemented through hole injection, thereby improving the device's ability to withstand surge current impacts.

Abstract: The present disclosure provides a power semiconductor device and a manufacturing method thereof. In order to provide a power semiconductor device with improved latch-up immunity but without increasing device power loss and costs, a hole current path in a fourth semiconductor region of a first conductivity type between a gate trench and a dummy gate trench is shortened by providing a first contact trench between two adjacent gate trenches, and providing a second contact trench between the gate trench and a dummy gate trench such that the width and depth of the second contact trench are respectively greater than those of the first contact trench. The effect of the hole current on the potential rise of the fourth semiconductor region of the first conductivity type is suppressed, thereby suppressing the latch-up effect, and enhancing the switching reliability.