Patents Assigned to JTAG Technologies
  • Method tester and circuit for applying a pulse trigger to a unit to be triggered
    Patent number: 5983378
    Abstract: A unit (108) to be triggered, for example a memory, receives data under the control of Boundary Scan Test (BST) logic, via a BST chain (110). The invention utilizes a pulse circuit (202) which generates a pulse trigger for the unit (108) on the basis of a stimulus presented via the BST chain (110). This saves time, because it is no longer necessary to supply the entire pulse trigger via the BST chain and the supply of the stimulus now suffices.
    Type: Grant
    Filed: October 10, 1996
    Date of Patent: November 9, 1999
    Assignee: JTAG Technologies
    Inventors: Hendrikus De Wit, Cornelis F. J. M. Stork