Abstract: Path determination constraints may be encoded in the form of a program having one or more instructions. Each of instructions may include an operation code, and operands (or pointers to locations where operands are stored). In this way, an extensible, interoperable way for a nodes (e.g., label-switching routers) to communicate constraints within a network is provided. Such constraints may be inserted (e.g., as one or more CONSTRAINT objects) into signaling messages (e.g., a PATH RSVP message). By enabling the signaling of constraints, the determination of constraint-based (label-switched) paths can be distributed among a number of (label-switching) routers or other nodes. Upon receiving a message with constraints (e.g.

Abstract: A system includes a controlling module for controlling a mobile device remotely A system includes a controlling module for controlling a mobile device remotely, wherein the controlling module includes a parental control module for controlling a mobile device used by a child.

Abstract: A method and apparatus for in-line processing a data packet while routing the packet through a router in a system transmitting data packets between a source and a destination over a network including the router. The method includes receiving the data packet and pre-processing layer header data for the data packet as the data packet is received and prior to transferring any portion of the data packet to packet memory. The data packet is thereafter stored in the packet memory. A routing through the router is determined including a next hop index describing the next connection in the network. The data packet is retrieved from the packet memory and a new layer header for the data packet is constructed from the next hop index while the data packet is being retrieved from memory. The new layer header is coupled to the data packet prior to transfer from the router.

Abstract: A method and apparatus for synchronizing components operating isochronously that are coupled by independent links. The apparatus includes a synchronization circuit having a first and second buffer, each including an input port coupled to an external link, an output port, a read pointer and a write pointer. The read pointer indicates a next location in a respective buffer to be read in transferring data out on the output port. The write pointer indicates a next location in the respective buffer to be written when receiving data on the input port and is configured to automatically increment upon receipt of a first data bit on a respective external link. A trigger circuit is coupled to each link for receiving external trigger signals. Each external trigger signal is included along with data transmitted on the link and indicates when data is present on a respective link. A counter is coupled to the trigger circuit. The counter includes a trigger input and a predefined delay period.

Abstract: A system prevents processor faults during the configuring of a programmable device. The system sets the processor into a reset mode, configures the programmable device using first configuration data, and determines whether the configuring using the first configuration data is successful. When the programmable device is not successfully configured, the system configures the programmable device using second configuration data and determines whether the configuring using the second configuration data is successful. The system releases the processor from the reset mode when the programmable device is successfully configured using the first or second configuration data or when the configuration of the programmable device using the second configuration data fails.

Abstract: A router for switching data packets from a source to a destination in a network in which the router includes a distributed memory. The distributed memory includes two or more memory banks. Each memory bank is used for storing uniform portions of a data packet received from a source and linking information for each data packet to allow for the extraction of the uniform portions of a data packet from distributed locations in memory in proper order after a routing determination has been made by the router.

Abstract: A method and apparatus for looking up a key associated with a packet to determine a route through a routing device, the method including, upon receipt of a key, forward traversing one or more nodes which make up a trie stored in a memory by evaluating at each node traversed a bit in the key as indicated by a bit-to-test indicator associated with each node. A value of the bit in the key determining the path traversed along the trie. The method includes locating an end node having a route and comparing the route to the key. If they match, destination information associated with the end node is outputted to guide the transfer of the packet through the routing device. If they do not match, the trie is traversed backwards to locate a best match for the key.

Abstract: A router for switching a data packet between a source and destination in a network including a plurality of input ports each including a data handler. The data handler divides a data packet into one or more fixed length cells. The router includes a plurality of output ports at least one of which is for routing the data packet to the destination and a memory divided into a plurality of memory banks. A input switch receives fixed length cells from the input ports and writes a single cell in a cell slot time span to each memory bank. An output switch routes cells received from the memory to an appropriate output port.