Abstract: Disclosed is a semiconductor device, including: a substrate of a first conductivity type that is a base for the semiconductor device; a high voltage junction field effect transistor, JFET, over the substrate, wherein the JFET including a plurality of parallel conductive layers; and a first conductive layer of the second conductivity type of the parallel conductive layers stretching over the substrate. On top of the first conductive layer of the second conductivity type is arranged a plurality of layers forming the parallel conductive layers with channels formed by a plurality of doped epitaxial layers of the second conductivity type with a plurality of gate layers of the first conductivity type on both sides thereof; wherein a lowermost layer of the first conductivity type is arranged in the form of consecutive dots with different lengths and distances between them.

Abstract: A semiconductor device is provided that includes an insulated gate field effect transistor series connected with a FET having several parallel conductive layers, a substrate of first conductivity type extending under both transistors, and a first layer of a second conductivity type overlies the substrate. Above this first layer are several conductive layers with channels formed by several of the first conductivity type doped epitaxial layers with layers of a first conductivity type on both sides. The uppermost layer of the device may be substantially thicker than the directly underlying parallel conductive layers. The JFET is isolated with deep poly trenches of second conductivity type on the source side. The insulated gate field effect transistor is isolated with deep poly trenches of the first conductivity type on both sides. A further isolated region is isolated with deep poly trenches of the first conductivity type on both sides.

Abstract: A semiconductor based integrated sensor device includes: a lateral insulating-gate field effect transistor (MOSFET) connected in series to the base of a vertical bipolar junction transistor (BJT) wherein the drain-drift-region of the MOSFET is part of the base-region of the BJT within the semiconductor substrate thus making electrical contact to the base of the BJT and the distance of the drain-drift-region of the MOSFET to the emitter of the BJT exceeds the vertical distance between the emitter and any buried layer, serving as collector, and the breakdown voltage of the device being determined by the BVCEO of the vertical BJT.

Abstract: The present invention provides a lateral IGBT transistor comprising a bipolar transistor and an IGFET. The lateral IGBT comprises a low resistive connection between the drain of the IGFET and the base of the bipolar transistor, and an isolating layer arranged between the IGFET and the bipolar transistor. The novel structure provides a device which is immune to latch and gives high gain and reliability. The structure can be realized with standard CMOS technology available at foundries.

Abstract: A semiconductor device includes a substrate, a body region adjoining the substrate surface, a source contact region within the body region, a drain contact region adjoining the substrate surface and being separated from the body region, a dual JFET gate region located between the body region and the drain contact region, and a lateral JFET channel region adjoining the surface of the substrate and located between the body and the drain contact regions. A vertical JFET gate region is arranged essentially enclosed by the body region, a vertical JFET channel region being arranged between the enclosed vertical JFET gate and the dual JFET gate regions, a reduced drain resistance region being arranged between the dual JFET gate and the drain contact regions, and a buried pocket located under part of the body region, under the dual JFET gate region and under the vertical JFET channel and reduced drain resistance regions.

Abstract: A semiconductor device includes a substrate, a body region adjoining the substrate surface, a source contact region within the body region, a drain contact region adjoining the substrate surface and being separated from the body region, a dual JFET gate region located between the body region and the drain contact region, and a lateral JFET channel region adjoining the surface of the substrate and located between the body and the drain contact regions. A vertical JFET gate region is arranged essentially enclosed by the body region, a vertical JFET channel region being arranged between the enclosed vertical JFET gate and the dual JFET gate regions, a reduced drain resistance region being arranged between the dual JFET gate and the drain contact regions, and a buried pocket located under part of the body region, under the dual JFET gate region and under the vertical JFET channel and reduced drain resistance regions.