Abstract: A method of separating a support substrate and a wafer adhered to the support substrate includes inserting a trigger member into a space between the support substrate and the wafer. The space opens on a gap region of the support substrate. The gap region is within an outer periphery of a base member of the support substrate. The base member has an adhesive layer contacting the wafer. The adhesive layer does not extend to an edge of the base member facing the gap region at the space. The wafer and the base member are contacted by the trigger member which promotes separation of the wafer and the support substrate from each other.

Abstract: An amplifier circuit includes, a first transistor and a first resistor connected in series between a power supply voltage and an output terminal. A second transistor and a second resistor are connected in series between the output terminal and a ground reference voltage. There is a first operational amplifier and a second operational amplifier. A first detection current corresponding to a voltage drop across first resistor is generated. A second detection current corresponding to a voltage drop across the second resistor is generated. A first replication circuit subtracts the second detection current from the first detection current. A third resistor conducts the current obtained by subtracting the second detection current from the first detection current.

Abstract: A battery pack includes a casing, a plurality of battery cells, and a first connector, for example. The casing includes a first outer wall and a protrusion that is provided on the first outer wall and protrudes outward from the first outer wall. The battery cells include an electrode terminal and are housed in the casing. The first connector is provided on the protrusion and is electrically connected to the electrode terminal.

Abstract: According to an embodiment, a power supply circuit is provided. The power supply circuit includes a switching transistor which is controlled to be ON/OFF by a PWM signal, and a mode switching control circuit configured to switch a control mode between peak current mode control and valley current mode control depending on the length of an ON time of the PWM signal which drives the switching transistor.

Abstract: A non-volatile memory controller for a solid state drive includes a soft-decision LDPC decoder. The soft-decision LDPC decoder includes a probability generation module. A processor reads collected statistics collated from decoded frames and tunes the performance of the soft-decision LDPC decoder performance. Additional parameters may also be taken into account, such as the scramble seed and the type of non-volatile memory. An asymmetry in errors may also be detected and provided to a hard-decision LDPC decoder to adjust its performance.

Abstract: According to one embodiment, a television receiver includes: a housing comprising a first opening; a speaker configured to be housed in the housing at a position where the speaker is exposed through the first opening; a cover comprising a plurality of second openings, the cover configured to be fixed to the housing on the first opening to cover the speaker; and a contact member in contact with the cover and configured to cover a part of the second openings.

Abstract: According to one embodiment, a semiconductor device includes a plurality of first interconnects, a second interconnect, a third interconnect, and a plurality of conductive members. The plurality of first interconnects are arranged periodically to extend in one direction. The second interconnect is disposed outside a group of the plurality of first interconnects to extend in the one direction. The third interconnect is provided between the group and the second interconnect. The plurality of conductive members are disposed on a side opposite to the group as viewed from the second interconnect. A shortest distance between the first interconnect and the third interconnect, a shortest distance between the third interconnect and the second interconnect, and a shortest distance between the first interconnects are equal. A shortest distance between the second interconnect and the conductive member is longer than the shortest distance between the first interconnects.

Abstract: A method of processing positron emission tomography (PET) information obtained from a PET detector having a plurality of detector regions, each detector region having at least one detector module and a corresponding regional collector, the method including the steps of receiving PET event information for a single PET event, the PET event information including energy information and crystal position information of the single PET event; receiving non-detector event information; generating an event list that includes (1) a PET event entry, the PET event entry including a fine time stamp, the energy information, and the crystal position information, and (2) a non-detector event entry that includes the received non-detector event information; and transmitting the generated event list to a computer for off-line processing.

Abstract: Certain embodiments provide a ferroelectric random access memory comprising a first buffer, a second buffer, a third buffer, a first controlling unit, a second controlling unit, a memory cell array, a sense amplifier circuit, and a third controlling unit. The first buffer outputs a first signal changed from a first value to a second value based on notification of power-down. The second buffer stops supply of inner clock signal with the change of the first signal from the first value to the second value. The third buffer receives an address signal corresponding to data to be read or written. The first controlling unit receives a command signal. The second controlling unit generates a basic signal that has a third value when the command signal indicates a bank active command and has a fourth value when the command signal indicates a precharge command and the first signal has the second value. The sense amplifier circuit reads data via a pair of bit lines from the memory cell corresponding to the address signal.

Abstract: The present invention provides a light transmission type solar cell excellent in both power generation efficiency and light transparency, and also provides a method for producing that solar cell. The solar cell of the present invention comprises a photoelectric conversion layer, a light-incident side electrode layer, and a counter electrode layer. The incident side electrode layer is provided with plural openings bored through the layer, and has a thickness of 10 nm to 200 nm. Each of the openings occupies an area of 80 nm2 to 0.8 ?m2, and the opening ratio is in the range of 10% to 66%. The transmittance of the whole cell is 5% or more at 700 nm wavelength. The incident side electrode layer can be formed by etching fabrication with a stamper. In the etching fabrication, a mono-particle layer of fine particles or a dot pattern formed by self-assembled block copolymer can be used as a mask.

Abstract: A couple 10 includes a valve seal member 71 (36) provided in a flow path between a valve 35 and a coupler main body 31 which can be opened and closed, and a container-inside-outside seal member (73) which is used as both a container seal member (73) for forming a seal between the container main body 31 and a valve holder 38 and a holder seal member (73) for forming a seal between the coupler main body 31 and the valve holder 38. By this arrangement, the number of the seal members can be reduced, processes for assembling can be simplified and the manufacturing cost can be saved. Mounting position of the holder 38 can be controlled by a mounting position control section 74 to enable sealing for maintaining energizing force by energizing means 39 constant and ensuring opening of the coupler as well as for securing the sealed state accurately.

Abstract: A liquid crystal display device includes a pair of substrates, a plurality of pixels arranged in a matrix and a static memory formed on the substrates. A bit signal corresponding to an image data is written and held in a static memory in the pixel. The polarity of the input bit signal is controlled. A liquid crystal voltage supplied to a liquid crystal layer arranged between the pair of substrates is generated by the bit signal. The polarity of the bit signal is controlled to alternate the liquid crystal voltage, and a transmittance of the liquid crystal layer is changed by supplying the alternated liquid crystal voltage.

Abstract: The semiconductor memory device includes: an inverter pair of a cross-coupled first and second inverters; a first transfer transistor including a front gate and a back gate connected to a first node to which an output terminal of the first inverter and an input terminal of the second inverter are connected; a second transfer transistor including a front gate and a back gate connected to a second node to which an output terminal of the second inverter and an input terminal of the first inverter are connected; a driver transistor whose gate is connected to the second node; and a read transistor including a front gate, a back gate connected to the second node, and a current path whose one end is connected to one end of a current path of the driver transistor.

Abstract: There are provided a screw-type cap which can secure necessary fastening torque (opening torque) even in a case of a container having a plug having a foremost end portion of a small diameter and also a safety cap which cannot be opened by only rotation and therefore has a child resistance effect. A safety cap 20 consists of a screw-type inner cap 21 and an outer cap 22 which is mounted in such a manner that it covers the inner cap 21 and can be rotated and can displace axially within a limited distance. The outer cap 22 can rotate integrally with the inner cap 21 by pushing down the outer cap 22 and rotate it while the outer cap 22 rotates idly by rotation only. A plug portion 8 is formed by projecting a plug 6 from a disk portion 7 which is in abutting engagement with a tip end portion of a mouth portion 2 of the container. The inner cap 21 has a small diameter portion 21c formed in the inner middle portion thereof.

Abstract: In a battery system, battery modules (3a, 3b) connected to each other in series respectively include: one or more single cells (3a1 to 3an, 3b1 to 3b-n) connected to one another in any one of series, parallel, and series-parallel; cell voltage switches (7a, 7b) for detecting voltages respectively of the one or more single cells; module monitoring control units (9a, 9b) each for monitoring the detected voltages respectively of the one or more signal cells; and communications level converter circuits (14a, 14b). The battery system includes a master unit (8a) for receiving information on the voltages respectively of the one or more single cells from the module monitoring control units via the communications level converter circuits. One of the communications level converter circuits includes a switch element (Q32) for transmitting a signal of a low-potential battery module to a high-potential battery module.

Abstract: A pouch with a spout includes a pouch body 1 formed by overlapping and thermally fusing both end portions, forming a seam, of a flexible film material and a spout 3 to be inserted between the film end portions of the pouch body 1 and then thermally fused together with the film end portions to the pouch body, wherein a stress dispersion patch 4 is bonded so as to cover partially both a spout seal portion 2 and a deformable film portion 5 so as to straddle a boundary portion between the spout seal portion 2 and the deformable film portion 5 facing an inner space of the pouch body 1.

Abstract: A non-volatile semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a first register group configured to store control data used for controlling memory operations; an adjusting data storage area defined in the memory cell array so as to store adjusting data used for adjusting the control data; and a second register group configured to store the adjusting data read from the adjusting data storage area.

Abstract: The other communication devices are prohibited to transmit the address initialization request for a prescribed period of time since one communication device transmitted the address initialization request for an address managed by a control protocol, so that the conflict of the initialization requests for the same address will not occur and the problem of assigning the address in overlap to the communication devices will not arise. Also, the other communication devices are prohibited to transmit the address server detection request packet for a prescribed period of time since one communication device transmitted the address server detection request packet, so that the conflict on the network by a plurality of address server detection requests will not occur, and it is possible to determine the MAC address server uniquely.

Abstract: A semiconductor apparatus includes: a first first-conductivity-type semiconductor layer; a second first-conductivity-type semiconductor layer provided on a major surface of the first first-conductivity-type semiconductor layer; a third second-conductivity-type semiconductor layer forming a periodic array structure in combination with the second first-conductivity-type semiconductor layer in a lateral direction generally parallel to the major surface of the first first-conductivity-type semiconductor layer; and a sixth first-conductivity-type semiconductor layer provided on the major surface of the first first-conductivity-type semiconductor layer in a termination section outside the periodic array structure. The second first-conductivity-type semiconductor layer has an impurity concentration varying in the lateral direction and the impurity concentration is minimized at a center in the lateral direction.

Abstract: An improved printed circuit board connection for connecting a first printed circuit board to a second printed circuit board in a manner that permits physical engagement at a different position than the electrical engagement, and a method for making the improved printed circuit board connection with precision in alignment. In one embodiment, the first printed circuit board includes an end portion configured to engage with a member of a connector on the second printed circuit board. The end portion and the member engage along concave portions of the end portion and convex portions of the member. When engaged, the end portion and the member align wires of the first printed circuit board with terminals of the connector.