Patents Assigned to Kabushiki Kaihsa Toshiba
  • Patent number: 9923192
    Abstract: According to one embodiment, there is provided a non-aqueous electrolyte secondary battery including a positive electrode, a negative electrode including a negative electrode active material layer, and a non-aqueous electrolyte. The negative electrode active material layer contains carbon dioxide and releases the carbon dioxide in the range of 0.1 ml to 5 ml per 1 g when heated at 200° C. for 1 minute.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: March 20, 2018
    Assignee: KABUSHIKI KAIHSA TOSHIBA
    Inventors: Shinsuke Matsuno, Hidesato Saruwatari, Dai Yamamoto, Asato Kondo, Hiromichi Kuriyama, Hideki Satake, Takashi Kuboki
  • Publication number: 20140288718
    Abstract: According to some embodiments, there is provided a power electronics device including: a controlling unit, a determining unit, a confirming unit and a determining unit. The controlling unit performs surveillance/control concerning an input/output of power to a power line with other power electronics devices connected via the power line. The determining unit determines a master device which is a subject of the surveillance/control and a slave device which is controlled by the master device, based on power characteristic information of the other power electronics devices from among the other power electronics devices and the power electronics device. The confirming unit confirms whether the master device and the slave device determined by the determining unit are matched with the master device and the slave device determined by the other power electronics devices. The determining unit permits a start of the surveillance/control when matching is determined by the confirming unit.
    Type: Application
    Filed: September 17, 2013
    Publication date: September 25, 2014
    Applicant: KABUSHIKI KAIHSA TOSHIBA
    Inventors: Yasuyuki NISHIBAYASHI, Keiichi TERAMOTO, Kotaro ISE, Yasuro SHOBATAKE, Ikuya AOYAMA, Yuki Yonezawa, Fumiaki Kanayama, Yusuke Doi, Shinya Murai
  • Publication number: 20130244143
    Abstract: According to one embodiment, an optimum imaging position detecting method includes acquiring an image of a predetermined area of a substrate surface, calculating, on the basis of the image of the predetermined area, peak intensity corresponding to a value obtained by subtracting average signal intensity of an area outside an intensity acquisition part from signal intensity of the intensity acquisition part, calculating variation of the peak intensity, executing acquiring the image of the predetermined area, calculating the peak intensity, and calculating the variation of the peak intensity at each of a plurality of imaging positions, and determining that a position of the maximum variation of the peak intensity is an optimum imaging position.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 19, 2013
    Applicant: Kabushiki Kaihsa Toshiba
    Inventors: Takeshi YAMANE, Tsuneo Terasawa
  • Patent number: 8217440
    Abstract: MOSFETs and methods of making MOSFETs are provided. According to one embodiment, a semiconductor device includes a substrate and a Metal-Oxide-Semiconductor (MOS) transistor that includes a semiconductor region formed on the substrate, a source region and drain region formed in the semiconductor region that are separated from each other, a channel region formed in the semiconductor region that separates the source region and the drain region, an interfacial oxide layer (IL) formed on the channel region into which at least one element disparate from Si, O, or N is incorporated at a peak concentration greater than 1×1019 atoms/cm2, and a high-k dielectric layer formed on the interfacial oxide layer having a high-k/IL interface at a depth substantially adjacent to the IL. In addition, at least one depth of peak density of the incorporated element(s) is located substantially below the high-k/IL interface.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: July 10, 2012
    Assignee: Kabushiki Kaihsa Toshiba
    Inventor: Yoshinori Tsuchiya
  • Patent number: 7446061
    Abstract: A semiconductor substrate with a groove is placed in a plasma generating reaction chamber. Silicon, oxygen and hydrogen containing gases are introduced into the reaction chamber as process gases. A ratio of a gas flow of the hydrogen containing gas except the silicon containing gas to a total gas flow of the silicon containing gas and the oxygen containing gas defines a first gas-flow ratio. A ratio of a gas flow of the oxygen containing gas to that of the silicon containing gas defines a second gas-flow ratio. The first and second gas-flow ratios establish a linear function for a critical condition. A cluster formation condition is set up by relatively increasing the first gas-flow ratio while relatively decreasing the second gas-flow ratio with respect to the critical condition. A cluster suppression condition is also set up by relatively decreasing the first gas-flow ratio while relatively increasing the second gas-flow ratio with respect to the critical condition.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: November 4, 2008
    Assignee: Kabushiki Kaihsa Toshiba
    Inventors: Hiroshi Sato, Rempei Nakata, Yukio Nishiyama, Taketo Matsuda
  • Patent number: 7351656
    Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: April 1, 2008
    Assignee: Kabushiki Kaihsa Toshiba
    Inventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
  • Patent number: 6304547
    Abstract: In case of a trouble in any unit network of a communications network system which comprises a plurality of unit networks, communications are relieved and reliability of communications is improved. The respective unit networks are connected through internetwork connection circuits, and communications are normally made on each unit network by a communication path formed by performing loopback of remote communication devices at both ends of the individual unit network. If a trouble such as a disconnection fault occurred in a certain unit network, the loopback of the internetwork connection circuit of the remote communication devices at both ends of the unit network having the trouble is relieved to form an alternate communication path, and this alternate communication path is used to keep the communications between local communication terminals adjacent to the troubled spot.
    Type: Grant
    Filed: July 13, 1998
    Date of Patent: October 16, 2001
    Assignee: Kabushiki Kaihsa Toshiba
    Inventors: Hidekazu Tsuruta, Kazuo Uwajima