Patents Assigned to Kabushiki Kaisa Toshiba
  • Publication number: 20180354121
    Abstract: According to one embodiment, a sorting apparatus includes a controller, a holding device, and a driver. The controller acquires holding position information corresponding to identification information of an article to be processed, and sets a holding position based on the holding position information. The holding device holds the article. The drive unit causes the holding device to hold the article in the holding position set by the controller, and moves the article held by the holding device.
    Type: Application
    Filed: May 30, 2018
    Publication date: December 13, 2018
    Applicants: KABUSHIKI KAISA TOSHIBA, Toshiba Infrastructure Systems & Solutions Corporation
    Inventor: Kentaro SEZAKI
  • Patent number: 7515386
    Abstract: There is provided a practical magnetoresistance effect element which has an appropriate value of resistance, which can be sensitized and which has a small number of magnetic layers to be controlled, and a magnetic head and magnetic recording and/or reproducing system using the same. In a magnetoresistance effect element wherein a sense current is caused to flow in a direction perpendicular to the plane of the film, a resistance regulating layer is provided in at least one of a pinned layer, a free layer and an non-magnetic intermediate layer. The resistance regulating layer contains, as a principal component, an oxide, a nitride, a fluoride, a carbide or a boride. The resistance regulating layer may be a continuous film or may have pin holes. Thus, it is possible to provide a practical magnetoresistance effect element which has an appropriate value of resistance, which can be sensitized and which has a small number of magnetic layers, while effectively utilizing the scattering effect depending on spin.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: April 7, 2009
    Assignee: Kabushiki Kaisa Toshiba
    Inventors: Yuuzo Kamiguchi, Hiromi Yuasa, Tomohiko Nagata, Hiroaki Yoda, Katsuhiko Koui, Masatoshi Yoshikawa, Hitoshi Iwasaki, Masashi Sahashi, Masayuki Takagishi
  • Patent number: 7076722
    Abstract: An ECC circuit (103) is located between I/O terminals (1040–1047) and page buffers (1020–1027). The ECC circuit (103) includes a coder configured to generate check bits (ECC) for error correcting and attach the check bits to data to be written into a plurality of memory cell areas (1010–1017), and a decoder configured to employ the generated check bits (ECC) for error correcting the data read out from the memory cell areas (1010–1017). The ECC circuit (103) allocates a set of 40 check bits (ECC) to an information bit length of 4224=(528×8) bits to execute coding and decoding by parallel processing 8-bit data, where data of 528 bits is defined as a unit to be written into and read out from one memory cell area (101j).
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: July 11, 2006
    Assignee: Kabushiki Kaisa Toshiba
    Inventor: Noboru Shibata
  • Publication number: 20030210893
    Abstract: By using program information, the amount of which to be transmitted is not fixed, and related information which is related to the expected amount of the main information, an area for recording main information is ensured in advance on a recording medium. This ensures a reliable recording of a program, the recording of which has already been reserved, without affecting any program which has already been recorded. In addition, even when a change occurs in related information before or after the start of recording information on the recording medium, an area assigned before the start of the recording can be changed corresponding to related information after the change.
    Type: Application
    Filed: June 16, 2003
    Publication date: November 13, 2003
    Applicant: KABUSHIKI KAISA TOSHIBA
    Inventors: Shigeyasu Natsubori, Toru Imai, Toshiya Takahashi, Shigeru Oyanagi
  • Patent number: 6181406
    Abstract: A liquid crystal display device has a liquid crystal panel wherein an opposite substrate includes a plurality of pillar-shaped spacers opposing scanning lines provided on an array substrate. The spacers have distal ends which contact the scanning lines with an opposite electrode of the opposing substrate being interposed between the distal ends and the scanning lines. Each of the distal ends of the spacers has a width smaller than the width of each scanning line. Pixel electrodes have notches which are formed in those of their side edges which are opposite to the scanning lines, such that the notches are located opposite to the distal ends of the spacers. The distance between the side edges of the pixel electrode and the scanning line opposing the side edges is larger at regions around the distal ends of the spacers than other regions.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: January 30, 2001
    Assignee: Kabushiki Kaisa Toshiba
    Inventors: Hirokazu Morimoto, Takaomi Tanaka, Tetsuya Nishino, Satoru Narioka
  • Patent number: 5841174
    Abstract: After a gate electrode of a high withstand voltage device is formed, a gate bird's beak is formed on the gate electrode by post-heat treatment. After a gate electrode of a low withstand voltage is formed, no post-heat treatment is performed and no gate bird's beak is formed. Ions are injected through a thermal oxidation film, thereby forming diffusion layers of the high withstand voltage device. Ions are directly injected in a semiconductor substrate, thereby forming diffusion layers of the low withstand voltage device. Accordingly, the impurity concentration in the diffusion layers of the low withstand voltage device is higher than that in the diffusion layers of the high withstand voltage device.
    Type: Grant
    Filed: October 5, 1995
    Date of Patent: November 24, 1998
    Assignee: Kabushiki Kaisa Toshiba
    Inventor: Norihisa Arai