Patents Assigned to Kabushiki Kaisha Nagasawa
  • Patent number: 4370623
    Abstract: An amplifier arrangement is provided which comprises first and second biasing power supply circuits, a push-pull amplifier comprising a pair of transistors, a DC amplifier having a non-inverting input terminal connected to a junction point at which one half of a predetermined potential fed from the first biasing power supply circuit is applied and an inverting input terminal connecting a feedback loop through which the output the amplifier is fedback, a second biasing power supply circuit having a junction point at which the output of the DC amplifier is applied, and means responsive to an output of the DC amplifier for applying either of the first and second predetermined potentials fed from the first and second biasing circuits in accordance with the amount of feedback from the output of the push-pull amplifier to produce an output signal showing a biasing current, whereby the output signal is applied to each base of the push-pull transistors so as to balance the half potential of the first biasing power su
    Type: Grant
    Filed: April 13, 1981
    Date of Patent: January 25, 1983
    Assignee: Kabushiki Kaisha Nagasawa
    Inventor: Hideki Nagasawa