Patents Assigned to Kabushiki Kaisha Toahiba
  • Publication number: 20020180030
    Abstract: There is disclosed a laminated-chip semiconductor device which comprises two chip-mounting substrates on each of which at least one semiconductor chip having a plurality of terminals for signals is mounted, and a plurality of chip connecting wirings electrically connected to the terminals for signals of the each semiconductor chip which are mounted on the chip-mounting substrates are formed in a same pattern, and which are laminated along a thickness direction, and one intermediate substrate which is arranged between the two chip-mounting substrates, and in which a plurality of interlayer connecting wirings electrically connected to each of the plurality of chip connecting wirings of the adjacent chip-mounting substrate are formed in a predetermined wiring pattern.
    Type: Application
    Filed: May 30, 2002
    Publication date: December 5, 2002
    Applicant: KABUSHIKI KAISHA TOAHIBA
    Inventors: Katsuhiko Oyama, Mitsuyoshi Endo, Chiaki Takubo, Takashi Yamazaki, Takashi Imoto
  • Patent number: 6034914
    Abstract: There is provided a semiconductor memory device which comprises a plurality of memory cells, a plurality of bit lines connected with the plurality of memory cells, a plurality of word lines connected with the plurality of memory cells, a plurality of data line pairs, a plurality of transfer gates for effecting controlled connection of the plurality of bit lines with the plurality of data lines, a plurality of column select lines for controlling conductibility of the plurality of the transfer gates, and a column select line drive circuit for simultaneously selecting and driving at least two of the plurality of column select lines corresponding to one-time column address input from the outside of the chip.
    Type: Grant
    Filed: October 28, 1998
    Date of Patent: March 7, 2000
    Assignee: Kabushiki Kaisha Toahiba
    Inventors: Tsuneo Inaba, Shinichiro Shiratake, Kenji Tsuchida
  • Patent number: 5204986
    Abstract: A radio apparatus having a battery saving function comprising an indicator for indicating that power is being supplied. An indicator is actuated in synchronization with the battery saving operation. In particular, a receiving circuit is intermittently triggered by the power supply and the indicator is intermittently triggered in synchronization with at least some of the power supply signals that trigger the receiving circuit. The period of actuation for the indicator may be less than the receiving circuit, which is intermittently actuated in accordance with a battery saving operation. Also, the indicator means may be actuated once for each n times that the receiving means is actuated.
    Type: Grant
    Filed: January 27, 1992
    Date of Patent: April 20, 1993
    Assignee: Kabushiki Kaisha Toahiba
    Inventors: Koichi Ito, Yasuo Oonishi