Patents Assigned to Kabushiki Kaisha Tobshiba
  • Patent number: 8823376
    Abstract: A magnetic resonance imaging apparatus includes a magnetic resonance data acquisition unit and a cerebrospinal fluid image data generation unit. The magnetic resonance data acquisition unit consecutively acquires a plurality of magnetic resonance data for generating a plurality of cerebrospinal fluid image data, each corresponding to a different data acquisition time, after a labeling pulse is applied. The cerebrospinal fluid image data generation unit generates the plurality of cerebrospinal fluid image data based on the plurality of magnetic resonance data.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: September 2, 2014
    Assignees: Kabushiki Kaisha Tobshiba, Toshiba Medical Systems Corporation
    Inventors: Yuichi Yamashita, Nobuyasu Ichinose, Shinichi Kitane
  • Patent number: 5774100
    Abstract: An array substrate of an LCD device includes a glass substrate, an n.times.m number of pixel electrodes arrayed in a matrix form on the glass substrate, an n-number of scanning lines formed along rows of the pixel electrodes on the glass substrate, an m-number of signal lines formed along columns of the pixel electrodes on the glass substrate, switching elements formed on the glass substrate and located adjacent to intersections of the scanning lines and signal lines, each switching element supplying a video signal from the signal line to the pixel electrode in response to a scanning signal supplied from the scanning line, and a test supporting circuit for sensing potentials of the scanning lines.
    Type: Grant
    Filed: September 26, 1996
    Date of Patent: June 30, 1998
    Assignee: Kabushiki Kaisha Tobshiba
    Inventors: Yoshiro Aoki, Youichi Masuda
  • Patent number: 5760425
    Abstract: The top-side (n-type) electrode and bottom-side (p-type) electrode of a Si chip with a p-n junction are pressed against a Cu cathode electrode and a Cu anode electrode via Mo plates respectively, thereby establishing electrical connection. The inner wall of a case is round and the Si chip is almost square. The top of the case is covered with ceramic, for example. A washer is a compression member. A chip frame holds the Si chip and Mo plates in compression positions and simultaneously determines their locations within the case. Specifically, the side face of the Si chip is not flush with the side face of each of the Mo plates. This enables the chip frame to make the creepage distance longer. Since the chip frame is a single chip frame without any joint, the creepage distance between the anode and cathode electrodes is defined by part of the chip frame that faces part of the surface of the Si chip and parts of the surfaces of the Mo plates sandwiching the Si chip between them.
    Type: Grant
    Filed: January 29, 1997
    Date of Patent: June 2, 1998
    Assignee: Kabushiki Kaisha Tobshiba
    Inventors: Ikuko Kobayashi, Michiaki Hiyoshi
  • Patent number: 5356830
    Abstract: A semiconductor device and its manufacturing method are provided in which an epitaxial silicon layer is formed by a selective epitaxial growth method over a semiconductor substrate and a polysilicon layer is formed by an ordinary deposition method on the epitaxial silicon layer and these layers and are formed over a semiconductor device in a continuous process within the same furnace for a CVD apparatus.
    Type: Grant
    Filed: December 17, 1990
    Date of Patent: October 18, 1994
    Assignee: Kabushiki Kaisha Tobshiba
    Inventors: Susumu Yoshikawa, Shuichi Samata, Satoshi Maeda, Shizuo Sawada
  • Patent number: 5293334
    Abstract: A first power source line is formed around a memory area having a memory cell array, column decoder, row decoder and sense amplifier formed therein. The first power source line is applied with a potential which is obtained by lowering a power source voltage supplied from the exterior. A second power source line is formed in the surrounding region of the first power source line. The second power source line is applied with a ground potential. A first peripheral circuit driven by a voltage between the lowered potential and the ground potential is disposed in an area between the first and second power source lines. The first peripheral circuit is a circuit used for the memory area. A third power source line is formed in the surrounding region of the second power source line. The third power source line is applied with a power source potential supplied from the exterior.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: March 8, 1994
    Assignee: Kabushiki Kaisha Tobshiba
    Inventor: Mitsuru Shimizu