Patents Assigned to KABUSHIKI KAISHA TOSHIBA and
  • Publication number: 20100148223
    Abstract: A semiconductor device includes an insulated-gate field-effect transistor which is disposed on a semiconductor substrate having an element formation plane in a (110) plane direction, and which has a channel length direction in a <?110> direction, and a first element isolation insulation film which is buried in a trench in an element isolation region of the semiconductor substrate and has a positive expansion coefficient, the first element isolation insulation film applying a compressive stress by operation heat to the insulated-gate field-effect transistor in the channel length direction.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 17, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Zhengwu Jin
  • Patent number: 7736290
    Abstract: A sheet folding apparatus, including: a stacker configured to stack a plurality of sheets; a first folding roller configured to rotate around a first axis; a second folding roller configured to rotate around a second axis which is in parallel with the first axis and biased to the first folding roller separably to make a nip together with the first folding roller therebetween; a blade unit configured to push a surface of the plurality of sheets stacked by the stacker, into the nip; a first support configured to support the blade unit and configured to move linearly in a common tangential direction of the first folding roller and the second folding roller at the nip; and a second support configured to support the blade unit, configured to move linearly in the common tangential direction when the blade unit passes a section between where the blade unit starts touching at the plurality of sheets and where the plurality of sheets approaches the nip, and configured to deviate the blade away from the common tangenti
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: June 15, 2010
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Tec Kabushiki Kaisha
    Inventors: Toshiaki Oshiro, Takahiro Kawaguchi, Tomomi Iijima
  • Patent number: 7738529
    Abstract: There is provided with there is provided with a wireless communication method using a frequency hopping scheme, which performs wireless communication with a different wireless communication apparatus by using a plurality of frequency bands, including: measuring interference quantities showing strength of interference signals in respective frequency bands; selecting a hopping pattern from a plurality of hopping patterns each having hopping densities set for the respective frequency bands on the basis of the interference quantities in the respective frequency bands, the hopping densities being the number of times that transmission is performed per unit time in the respective frequency bands; notifying the different wireless communication apparatus of the selected hopping pattern; and communicating with the different wireless communication apparatus by using the selected hopping patter.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomoya Horiguchi
  • Patent number: 7739443
    Abstract: The present invention provides a memory controller which includes a host interface connected to a host apparatus and receives a first data write-in unit of reception data, a memory interface connected to nonvolatile semiconductor memory in which is written a second data write-in unit of data larger than the first data write-in unit of data, and transmits the first data write-in unit of write-in data, and a central processing unit, which writes the reception data in a temporary write-in block of the nonvolatile semiconductor memory via the memory interface, reads out from the temporary write-in block the write-in data corresponding to area data when a total amount of reception data received by the host interface has reached amount of the second data write-in unit of the area data, and writes the area data including the read-out write-in data in a target block different from the temporary write-in block.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideo Aizawa
  • Patent number: 7738124
    Abstract: An image forming apparatus performs a user authentication process and performs a private print process according to a request from an authenticated user. When the user requests interruption of the private print which is now performed or it is detected that the user has left a place near the image forming apparatus while the private print is being performed, the image forming apparatus interrupts the private print which is now performed and stores a print state at the interruption time. Further, the image forming apparatus performs a user authentication process and re-starts the private print which is interrupted in response to a re-start request from the authenticated user.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: June 15, 2010
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Tec Kabushiki Kaisha
    Inventors: Kazuhiro Ogura, Shinji Makishima, Akihiro Mizutani, Toshihiro Ida
  • Patent number: 7736715
    Abstract: In a single-sided, recordable/rewritable phase change optical recording medium having one or more layers, an interface layer adjacent to a phase change optical recording film contains at least Zr (zirconium), O (oxygen), and N (nitrogen), and further contains one or both of Y (yttrium) and Nb (niobium).
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsukasa Nakai, Noritake Oomachi, Sumio Ashida, Naomasa Nakamura, Keiichiro Yusu, Yasuhiro Satoh
  • Patent number: 7738239
    Abstract: According to one embodiment, an electronic apparatus comprises: a casing comprising a circuit module; a keyboard mounting portion on which a keyboard is detachably mounted, and a cover detachably covering the opening. The key board mounting portion comprises an opening which allows a wiring electrically connecting the keyboard and the circuit module to be passed therethrough. An area of the opening is equal to or less than half of an area of the keyboard mounting portion.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Yokote, Kouji Abe, Tomomi Murayama, Atsushi Tatemichi
  • Patent number: 7738302
    Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noboru Shibata, Tomoharu Tanaka
  • Patent number: 7739560
    Abstract: A test interface receives a test command designating execution of a test for a memory cell. The test storage circuit stores test information necessary to execute the test. The test storage circuit includes an erasable programmable storage unit. The decoder decodes the test command input to the test interface, and selects the test information stored in the test storage circuit. The sense amplifier reads out, from the test storage circuit, the test information selected by the decoder. The holding circuit holds the test information read out by the sense amplifier. The control circuit controls a test operation of checking whether the memory cell normally operates, on the basis of the test information held in the holding circuit. The defect storage circuit is formed for the memory cell, and stores fail information indicating that the memory cell is defective if the memory cell does not normally operate in the test operation.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hidetoshi Saito
  • Patent number: 7738041
    Abstract: According to one embodiment, a video signal processor has a moving block determining module, a vertical edge detector, a moving block number counter, a moving field determining module, a pulldown pattern detector, and a pulldown signal determining module. The moving block determining module divides each field configuring an input video signal into a plurality of blocks, and determines a motion of a block within the plurality of blocks, the block of which the motion is determined having a same spatial position within two fields adjacent to each other. The vertical edge detector detects a vertical edge within each of the plurality of blocks in the each field. The moving block number counter counts a number of moving blocks excluding a block having the vertical edge within a screen based on the detection result of the vertical edge detector and the determination result of the moving block determining module.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Himio Yamauchi
  • Patent number: 7737041
    Abstract: A semiconductor device comprises a semiconductor layer including a plurality of paralleled linear straight sections extending in a first direction. The layer also includes a plurality of connecting sections each having a width in the first direction sufficient to form a wire-connectable contact therein and arranged to connect between adjacent ones of the straight sections in a second direction. The connecting sections have respective ends formed aligned with a first straight line parallel to the second direction.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Hideaki Aochi, Takayuki Okamura
  • Patent number: 7738410
    Abstract: According to one embodiment, a server apparatus includes a storage module stores information to execute paging of which the broadcast is not completed yet for paging using the recording module, a determination module determines whether or not to execute paging of information in which a paging request has been already recorded in the recording module, a detector detects a storage information amount of the paging stored in the storage module, and a report module reports the storage information amount detected by the detector to a terminal of a paging request origin.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Emi Senga
  • Patent number: 7738248
    Abstract: According to one embodiment, an electronic device includes a heat generating part housed inside a cabinet and a loop heat pipe housed inside the cabinet, which includes an internal flow path having a loop shape in which a working fluid is sealed. The loop heat pipe further includes a heat receiving unit, a heat radiating unit, a vapor flow path which allows a gasified portion of the working fluid to flow from the heat receiving unit towards the heat radiating unit, a liquid returning flow path which allows a liquefied portion of the working fluid to flow from the heat radiating unit towards the heat receiving unit, and a wick provided at a position adjacent to the vapor flow path inside the liquid returning flow path. The wick also serves as a partition portion which partitions the vapor flow path and the liquid returning flow path from each other.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kentaro Tomioka
  • Patent number: 7738220
    Abstract: A magnetoresistance effect element, comprising a nonmagnetic spacer layer, first and second ferromagnetic layers separated by the nonmagnetic spacer layer, the first ferromagnetic layer having a magnetization direction at an angle relative to a magnetization direction of the second ferromagnetic layer at zero applied magnetic field, the magnetization of the first ferromagnetic layer freely rotating in a magnetic field signal, a magnetoresistance effect-improving layer comprising a plurality of metal films and disposed in contact with the first ferromagnetic layer so that the first ferromagnetic layer is disposed between the nonmagnetic spacer layer and the magnetoresistance effect-improving layer, one of the plurality of metal films disposed in contact with the first ferromagnetic layer contains metal element of not solid solution with metal element of the first ferromagnetic layer and a nonmagnetic underlayer or a nonmagnetic protecting layer disposed in contact with the magnetoresistance effect-improving la
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Fukuzawa, Yuzo Kamiguchi, Katsuhiko Koui, Shin-ichi Nakamura, Hitoshi Iwasaki, Kazuhiro Saito, Hiromi Fuke, Masatoshi Yoshikawa, Susumu Hashimoto, Masashi Sahashi
  • Patent number: 7736446
    Abstract: A method for manufacturing a lanthanum oxide compound on a substrate includes: setting the number of H2O molecule, the number of CO molecule and the number of CO2 molecule to one-half or less, one-fifth or less and one-tenth or less per one lanthanum atom, respectively, the H2O molecule, the CO molecule and the CO2 molecule being originated from an H2O gas component, a CO gas component and a CO2 gas component in an atmosphere under manufacture; and supplying a metal raw material containing at least one selected from the group consisting of lanthanum, aluminum, titanium, zirconium and hafnium and an oxygen raw material gas simultaneously for the substrate under the condition that the number of O2 molecule are set to 20 or more per one lanthanum atom, thereby manufacturing the lanthanum oxide compound on the substrate.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Takashima, Koichi Muraoka
  • Patent number: 7736781
    Abstract: A proton conductive polymer comprising a repeating unit represented by formula (1): wherein R1, R2 and R3 each independently represents a substituent; and V, W and X each independently represents a positive integer.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomoaki Arimura
  • Patent number: 7738276
    Abstract: A first region having a first pattern which includes a first minimum dimension, a second region having a second pattern which includes a second minimum dimension larger the first minimum dimension, the second region being arranged adjacent to the first region, wherein a boundary between the first region and the second region is sectioned by a width which is twice of more of a minimum dimension which exists in an adjacent region.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kosuke Yanagidaira, Takuya Futatsuyama, Toshiya Kotani
  • Patent number: 7736005
    Abstract: In a one-dimensional IP (vertical disparity discarding system), it is made possible to obtain a perspective projection image with no distortion or reduced distortion. A stereoscopic display device is provided with a display device including a display plane in which pixels are arranged flatly in a matrix shape; and a parallax barrier including a plurality of apertures or a plurality of lenses and being configured to control directions of rays from the pixels such that a horizontal disparity is included but a vertical disparity is not included.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Saishu, Yuzo Hirayama
  • Patent number: D617915
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: June 15, 2010
    Assignees: Toshiba Lighting & Technology Corporation, Kabushiki Kaisha Toshiba
    Inventors: Asuka Wada, Aiko Hiraga
  • Patent number: D617920
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: June 15, 2010
    Assignees: Toshiba Lighting & Technology Corporation, Kabushiki Kaisha Toshiba
    Inventors: Aiko Hiraga, Asuka Wada