Patents Assigned to KABUSHIKI KAISHA TOSHIBA and
  • Publication number: 20200285445
    Abstract: According to the embodiments, a semiconductor device includes: an adder configured to generate positive multiple data of the multiplicand which is used for a plurality of the multiplication in plurality and does not include a value of 2n (n is a positive integer) of the multiplicand; a Wallace tree circuit provided in each of the multiplier circuits and configured to operate a sum of a plurality of partial products by using a plurality of adders; and a selection circuit provided in each of the multiplier circuits and configured to select, according to a plurality of bits selected from the multiplier, data falling in a multiple of one of the multiplicand, data of 2n of the multiplicand, and the positive multiple data from the adder in order to output as one partial product of the plurality of partial products to the Wallace tree circuit.
    Type: Application
    Filed: September 10, 2019
    Publication date: September 10, 2020
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Nobuaki SAKAMOTO
  • Publication number: 20200283916
    Abstract: According to one embodiment, an electrolytic cell includes: a housing for retaining an electrolytic solution; a diaphragm that partitions an interior of the housing into an anode-side cell and a cathode-side cell; an anode electrode that is provided in the anode-side cell and has most of a surface in contact with an anode-side gas phase; and a cathode electrode that is provided in the cathode-side cell and has most of a surface in contact with a cathode-side gas phase. According to the other embodiment, a hydrogen production apparatus according to the present embodiment includes: an electrolytic solution tank that retains an electrolytic solution; and a pump that supplies the electrolytic solution between the anode electrode and the cathode electrode from the electrolytic solution tank.
    Type: Application
    Filed: February 5, 2020
    Publication date: September 10, 2020
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hirotoshi Murayama
  • Publication number: 20200284845
    Abstract: A battery charger as an embodiment of the present invention includes a charger/discharger, a measurer, an estimator, a determinator, and an outputter. The charger/discharger can charge and discharge a connected battery. The measurer measures a voltage and current of the battery during charging and generates measurement data. The estimator estimates a deterioration state of the battery on the basis of the measurement data. The determinator determines whether or not the battery is usable, on the basis of the estimated deterioration state of the battery. The outputter outputs information about the determination as to whether or not the battery is usable.
    Type: Application
    Filed: September 6, 2019
    Publication date: September 10, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yumi FUJITA, Tomokazu MORITA, Nobukatsu SUGIYAMA
  • Publication number: 20200286517
    Abstract: According to one embodiment, a magnetic disk device includes a disk including two first servo sectors and at least a second servo sector, a head, and a controller, wherein the first servo sector includes burst data and a first data pattern written before the circumferential direction of the burst data, the second servo sector includes the burst data, the first data pattern, and a second data pattern written after the circumferential direction of the burst data, a first frequency of the first data pattern is different from a second frequency of the second data pattern, and a first length of the first data pattern is different from a second length of the second data pattern.
    Type: Application
    Filed: September 12, 2019
    Publication date: September 10, 2020
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation, Toshiba Electronic Devices & Storage Corporation
    Inventor: Naoki Tagami
  • Publication number: 20200287531
    Abstract: According to one embodiment, a semiconductor integrated circuit includes a normally-on type first switching element that has a source, a drain, and a gate, a normally-off type second switching element that has a drain that is connected to the source of the first switching element, a gate that is supplied with a driving signal, and a source, a resistor that is connected between the gate of the first switching element and the source of the second switching element, a first capacitor that is connected in parallel to the resistor, and a second capacitor between the gate and the source of the first switching element.
    Type: Application
    Filed: July 31, 2019
    Publication date: September 10, 2020
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hideaki Majima
  • Publication number: 20200288058
    Abstract: A multi-view optical system includes an optical element. The optical element is configured to direct, in a predetermined direction, a first polarization component of a light beam coming from a first visual field, and a second polarization component, which is different from the first polarization component, of a light beam coming from a second visual field different from the first visual field.
    Type: Application
    Filed: August 30, 2019
    Publication date: September 10, 2020
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ohno, Hiroya Kano
  • Publication number: 20200285536
    Abstract: A semiconductor device of an embodiment includes a main circuit configured to perform a predetermined operation to an input signal to output an output signal, an inverse operation circuit configured to receive the output signal of the main circuit as an input, and perform an inverse operation of the predetermined operation by using the output signal to output an inverse operation result signal, and a comparison circuit configured to compare the input signal and the inverse operation result signal, and output a predetermined signal when the input signal and the inverse operation result signal do not coincide with each other.
    Type: Application
    Filed: September 5, 2019
    Publication date: September 10, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Shigeru NAKAJIMA
  • Publication number: 20200288116
    Abstract: An image processing apparatus of an embodiment is an image processing apparatus including a first image processing section configured to perform image processing for frames which are designated as processing target frames, a failure diagnosis processing section configured to perform failure diagnosis of the first image processing section at each frame period, and a failure diagnosis control section configured to control execution of the failure diagnosis processing section. The failure diagnosis control section includes a signal selecting section that gives notice of a failure diagnosis permission state which is a state where the first image processing section is capable of executing failure diagnosis. The signal selecting section outputs a failure diagnosis start permission signal at a time point of receiving a pseudo image processing completion signal from a failure diagnosis processing start timing generating section if the input frame is a processing non-target frame.
    Type: Application
    Filed: September 10, 2019
    Publication date: September 10, 2020
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yoshiharu Uetani, Masami Ashino
  • Publication number: 20200284744
    Abstract: The embodiments provide a method making it possible to safely and inexpensively measure concentrations of combustible gases, such as methanol, at room temperature even in high concentration atmospheres, and also provide a sensor making it possible to carry out the above measurement method.
    Type: Application
    Filed: September 6, 2019
    Publication date: September 10, 2020
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Naito, Naomi Shida
  • Publication number: 20200285992
    Abstract: According to an embodiment, a machine learning model compression system includes a memory and a hardware processor. The hardware processor is coupled to the memory and configured to: analyze an eigenvalue of each layer of a machine learning model by using a data set and the machine learning model, the machine learning model having been learned based on the data set; determine a search range of a compressed model based on a count of eigenvalues, each of which is used for calculating a first value and causes the first value to exceed a predetermined threshold; select a parameter for determining a structure of the compressed model included in the search range; generate the compressed model by using the parameter, and judge whether the compressed model satisfies one or more predetermined restriction conditions or not.
    Type: Application
    Filed: August 27, 2019
    Publication date: September 10, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takahiro TANAKA, Atsushi YAGUCHI, Ryuji SAKAI, Masahiro OZAWA, Kosuke HARUKI
  • Publication number: 20200285860
    Abstract: An image processing apparatus including a plurality of transfer units, a data storage, an image processing processor, and a test circuit. A plurality of captured image data are respectively assigned to the plurality of transfer units and the plurality of transfer units transfer the assigned image data. The data storage unit stores the plurality of image data which are transferred by the plurality of transfer units. The image processing processor performs image processing on the plurality of image data which are stored in the data storage unit. The test circuit tests the image processing processor in a period during which the image data are not input from the data storage unit to the image processing processor.
    Type: Application
    Filed: August 12, 2019
    Publication date: September 10, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventor: Yutaka YAMADA
  • Patent number: 10771446
    Abstract: According to one embodiment, when a control unit is notified of information in at least one second signal received by one of first and second wireless communication units after the control unit provides the second wireless communication unit with a command to transmit a first signal containing first address information and before a waiting time elapses and when the at least one second signal contains second address information assigned to an authentication apparatus having received the first signal, then the control unit provides the first wireless communication unit with a command to transmit a third signal for a connection request with the second address information set in a destination address.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: September 8, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko Adachi, Seiichiro Horikawa, Koji Akita, Ryoko Matsuo
  • Patent number: 10771688
    Abstract: According to one embodiment, an image processing device that processes a first image and a second image captured by a camera includes a first circuit, a second circuit and a third circuit. The first circuit determines a first position of a first reference line and a second position of a second reference line in at least one of the first image and the second image. The second circuit determines a image deformation reduction parameter based on a line width from a first reference point on the first reference line at the first position to a second reference point on the second reference line at the second position. The third circuit reduces image deformation in the first image or the second image based on the image deformation reduction parameter.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: September 8, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Yutaka Oki
  • Patent number: 10770095
    Abstract: According to one embodiment, a recording density setting method includes performing first process and performing second process. The first process including recording and reading data on and from a disk medium of a magnetic disk device, and acquiring first information for setting the read data to satisfy a certain quality criterion. The first information represents a first shape of a first plurality of unit regions. Each of the a first plurality of unit regions is a recording region of a unit capacity. The second process includes acquiring second information representing a second shape of the first plurality of unit regions, and setting a recording density on the basis of the second information. The second shape is formed by adding margin regions having the same area to the first plurality of unit regions of the first shape.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: September 8, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Kazuto Kashiwagi
  • Patent number: 10770995
    Abstract: According to one embodiment, there is provided a control device including a detecting circuit, a control circuit and a drive circuit. The detecting circuit detects changes in a current flowing between a node and a smoothing circuit, the node being to which a DC brush motor, a power supply circuit and the smoothing circuit can be electrically connected via respective different lines. The control circuit generates a control signal to control rotation speed of the DC brush motor according to the detected changes in the current. The drive circuit drives the DC brush motor according to the control signal.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: September 8, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hideki Kimura
  • Patent number: 10771057
    Abstract: A semiconductor device of embodiments includes a first normally-off transistor having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode electrically connected to the second electrode via a first wiring, a fourth electrode, and a second control electrode, a second normally-off transistor having a fifth electrode, a sixth electrode electrically connected to the third electrode via a second wiring, and a third control electrode, a first diode having a first anode electrically connected to the second control electrode and a first cathode electrically connected to the third electrode, and a capacitor having a first end portion connected to the first anode and the second control electrode and a second end portion.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: September 8, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Akira Yoshioka, Toru Sugiyama, Masaaki Iwai, Naonori Hosokawa, Masaaki Onomura, Hung Hung, Yasuhiro Isobe
  • Patent number: 10770208
    Abstract: A high performance permanent magnet is provided. The permanent magnet includes a composition represented by a composition formula: RpFeqMrCutCo100-p-q-r-t, and a metallic structure including cell phases having a Th2Zn17 crystal phase and Cu-rich phases having higher Cu concentration than the cell phases. An average diameter of the cell phases is 220 nm or less, and in a numeric value range from a minimum diameter to a maximum diameter of the cell phases, a ratio of a number of cell phases having a diameter in a numeric value range of less than upper 20% from the maximum diameter is 20% or less of all the cell phases.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: September 8, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke Horiuchi, Shinya Sakurada, Keiko Okamoto, Masaya Hagiwara, Tsuyoshi Kobayashi, Masaki Endo, Tadahiko Kobayashi, Naoyuki Sanada
  • Patent number: 10770902
    Abstract: According to one embodiment, a solar cell system includes a first solar cell including a first terminal and a second terminal, a second solar cell including a third terminal and a fourth terminal, and a voltage converter including a fifth terminal and a sixth terminal. The third terminal is electrically connected to the first terminal. The fifth terminal is electrically connected to the fourth terminal. The voltage converter causes a second absolute value to be smaller than a first absolute value. The first absolute value is of a difference between a first potential difference and a second potential difference. The first potential difference is between the first and second terminals. The second potential difference is between the first and fourth terminals. The second absolute value is of a difference between the first and third potential differences. The third potential difference is between the first and sixth terminals.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: September 8, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Soichiro Shibasaki, Mutsuki Yamazaki, Sara Yoshio, Naoyuki Nakagawa, Kazushige Yamamoto, Yuya Honishi
  • Patent number: 10770111
    Abstract: In a disk drive, when an off-track error occurs during a sequential disk access operation that spans multiple contiguous data tracks, efficient recovery is performed. In an embodiment, the disk access operation (e.g., reading from or writing to a disk) is attempted for all sectors of the sequential disk access operation. The disk access operation is then attempted again for sectors associated with any off-track errors that occurred during the disk access operation. In another embodiment, when an off-track error occurs during a sequential write operation in a shingled magnetic recording drive, the data originally targeted to be written to a first portion is written to a second portion of the data track that follows the first portion. Since no additional revolutions of the disk are needed for data associated with the sequential write operation to be written to the disk.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: September 8, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Fernando A. Zayas
  • Patent number: 10769534
    Abstract: An evaluation target of interest extraction apparatus of one embodiment extracts a plurality of items for each piece of text information. When the items include an item which matches an evaluation target expression or related expression, the apparatus allocates the evaluation target expression or that of the related expression to the text information as an evaluation target item. The apparatus distinguishes a class from a change in numeric information related to the evaluation target item, and allocates the class to the text information. The apparatus generates a class-attached transaction including the evaluation target item, the items, and the class. The apparatus discovers a pattern from a set of the transactions.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: September 8, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Solutions Corporation
    Inventors: Shigeaki Sakurai, Kyoko Makino, Hiroyuki Suzuki