Patents Assigned to KABUSHIKI KAISHA TOSHIBA and
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Patent number: 5372015Abstract: A controller for controlling an air conditioner comprises a room temperature sensor for measuring a room temperature, a room temperature change computation circuit for computing a difference between the room temperature and a set temperature, an outdoor temperature sensor for measuring an outdoor temperature, a neural network for computing load on the air conditioner according to the temperature change, outdoor temperature, and room temperature, and a controller for controlling, according to the computed load, the operation frequency of a coolant compressor by controlling a compressor motor through a variable frequency circuit, thereby speedily bringing the room temperature to the set temperature and stably maintaining the room temperature at the set temperature. The neural network learns various operation characteristics of a refrigerating cycle of the air conditioner, and according to a result of the learning, controls the air conditioner.Type: GrantFiled: July 2, 1992Date of Patent: December 13, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Kazuo Suzuki, Tetsuo Sano
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Patent number: 5373292Abstract: An integrating D-A/A-D converter includes a reference value generation circuit for generating at least one reference value relating to voltage or current, a control circuit for carrying out switching between a digital or analog input and the reference value every predetermined time to connect a switched one to thereby control an integral time, and an integration circuit for respectively integrating an analog value corresponding to the digital or analog input and the reference value switched in sequence every predetermined time and delivered through the control circuit to output an integral value for providing a digital or analog output.Type: GrantFiled: July 29, 1993Date of Patent: December 13, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Akira Yasuda
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Patent number: 5371710Abstract: A memory cell array, which is one of a plurality of divisional memory cell arrays, is selected by an address signal. One of the word lines incorporated in the memory cell array is selected by a row decoder. An OR circuit is supplied with a control signal for setting a burn-in test mode, and with the address signal for selecting the memory cell array. In the burn-in test mode, since the level of the control signal becomes high, the output level of the OR circuit becomes high irrespective of the address signal. Thus, the overall memory cell arrays are simultaneously selected, and hence more word lines than those accessed in a normal operation mode are simultaneously accessed.Type: GrantFiled: April 16, 1993Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Masaki Ogihara
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Patent number: 5371683Abstract: Disclosed is an LSI design support system for making a functional design of LSI using a graphic input method. This system comprises a state transition diagram preparation portion for preparing a state transition diagram, state transition table preparation portion for preparing a state transition table, and a state-operation circuit diagram preparation portion for preparing a state-operation circuit diagram. Data from these preparation portions are examined therebetween and the results are displayed at the same time on a picture plane so that a designer can efficiently make a design on circuit operation including its state transition. Also disclosed is another LSI design support system.Type: GrantFiled: October 3, 1991Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Fukazawa, Kunihiko Yamagishi, Eiichi Yano, Masatoshi Sekine
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Patent number: 5371862Abstract: A program execution control system is provided for a processing unit of a computer. An exclusive register has a plurality of 1-bit flag in which true and false data can be individually set and which can individually specify a flag for determining whether execution of each instruction in the program is canceled or not for each instruction.Type: GrantFiled: February 26, 1992Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Shinichiro Suzuki, Yoichiro Takeuchi
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Patent number: 5371693Abstract: If there is neither a key input from a keyboard nor a command input from a CPU within a predetermined period of time, a keyboard controller generates an NMI request for sleep control. The CPU executes the NMI request in accordance with an NMI routine stored in a ROM. If the CPU is in an idle state, a sleep mode is set.Type: GrantFiled: October 13, 1992Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Masayo Nakazoe
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Patent number: 5371664Abstract: The power conversion system of this invention comprises line-commutated power converting means in which a line-commutated power conversion circuit that performs line-commutated commutation and a coupling diode are coupled to form a DC circuit and for converting DC power into AC power or AC power into DC power. Further, the system comprises self-commutated power converting means, in which a self-commutated power conversion circuit is coupled to the coupling diode in order to form a DC circuit and for reducing reactive power, or the reactive power and harmonics generated by the line-commutated converting means. Accordingly, their respective strengths can be made use of and their mutual weaknesses can complement each other.Type: GrantFiled: November 4, 1992Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Nagataka Seki
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Patent number: 5371702Abstract: In response to a plurality of address signal input from the outside in sequence, an erase information inputting section controls an erase information holding section corresponding to the batch erase block to be erased so as to hold an erase information data. By repeating this operation in sequence, the erase information data are stored in the erase information holding sections corresponding to the plural batch erase blocks to be erased. Successively, on the basis of the erase information data stored in the erase information holding sections, block erasing sections are activated to erase all the nonvolatile memory cells of each of the corresponding blocks where the erase information data are held.Type: GrantFiled: March 5, 1993Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Hiroto Nakai, Hideo Kato, Kaoru Tokushige, Masamichi Asano, Kazuhisa Kanazawa, Toshio Yamamura
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Patent number: 5371371Abstract: A magnetic immersion field emission electron gun has a vacuum vessel having a central axis in a predetermined direction, a cathode arranged along the central axis of the vacuum vessel for generating an electron beam, an anode for forming an electron beam path by accelerating a generated electron beam in the central axis direction, an electrostatic lens arranged between the cathode and anode for generating an electric field which focuses an accelerated electron beam toward the central axis, a magnetic field generating element arranged around the electron beam path for generating a magnetic field for focusing the electron beam in order to preventing a diameter of the electron beam from expansion by an aberration of the electrostatic lens, and a moving mechanism for moving the magnetic field generating element at a position where a peak point of a strength of the magnetic field generated by the magnetic field generating element coincides with a portion where the aberration of the electrostatic lens becomes mostType: GrantFiled: August 27, 1993Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Yuichiro Yamazaki, Motosuke Miyoshi, Takamitsu Nagai
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Patent number: 5371865Abstract: A computer having a main memory for storing a plurality of data, a cache memory for temporarily storing a portion of the plurality of data, a processor for accessing data stored in the cache memory and processing the data according to instructions. The processor has an access instruction combined with a preload instruction, and an access instruction only for accessing data, and includes indicator circuitry for indicating a preload condition to the cache memory when the processor accesses data from the cache memory according to the access instruction combined with the preload instruction. The cache memory preloads data to be accessed next by the processor from the main memory when the processor indicates the preload condition.Type: GrantFiled: June 14, 1991Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Aikawa, Kenji Minagawa, Mitsuo Saito
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Patent number: 5371365Abstract: There is provided a scanning probe microscopy comprising a probe 6 situated to face the surface of an sample 1, a first piezoelectric element 8 for moving the sample 1 and the probe 6 relative to each other in a first direction perpendicular to the surface of the sample, and second and third piezoelectric elements 3 and 4 for moving the probe and the sample relative to each other in second and third directions perpendicular to the first direction, thereby enabling the probe to scan the surface of the sample, wherein at least one of the first to third piezoelectric elements 8, 3 and 4, which is closest to the sample 1, is formed of a single crystal.Type: GrantFiled: February 1, 1993Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Miyoko Watanabe, Koichi Mizushima, Tomio Ono, Tsuyoshi Kobayashi, Satoshi Itoh
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Patent number: 5371573Abstract: An image forming system for forming an image on a sheet includes a first receiving section and a second receiving section. A first transporting section transports the sheet-to the first receiving section. A second transporting section transports the sheet to the second receiving section. A selecting section selects either the first receiving section or the second receiving section. A detector detects that the second receiving section is in an abnormal condition while the selecting section selects the second receiving section. The selection of the selecting section is changed from the second receiving section to the first receiving section corresponding to the detection of the detector. The second transporting section is driven until all the sheets in the second transporting section are transported to the second receiving section.Type: GrantFiled: March 25, 1993Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Koji Kagaya, Kesao Shindo, Takashi Matsuoka, Satoshi Onuma
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Patent number: 5371486Abstract: A transformer core includes a first core member formed by laminating grain oriented 3% silicon steel sheets and second core members disposed at respective sides of the first core member in the direction of lamination so that the first core member is sandwiched by the second core members. Each second core member is formed by laminating non-oriented 6.5% silicon steel sheets. A commercial frequency component of magnetic fluxes mainly passes through the second core members such that an amount of noise caused by a higher harmonic component is reduced.Type: GrantFiled: November 25, 1992Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Kazuo Yamada, Eiji Shimomura, Kenshi Ishihara, Miyoshi Horiuchi
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Patent number: 5371024Abstract: A semiconductor device has a semiconductor substrate of the first conductivity type, a gate electrode buried in a groove formed in an element region of the substrate, first source and drain regions of the second conductivity type formed in surface regions of the semiconductor substrate on either side of the gate electrode, and second source and drain regions each having a concentration higher than that of each of the first source and drain regions, the second source and drain regions being formed in the surface regions of the semiconductor substrate on either side of the gate electrode, spaced away from the gate electrode, and adjacent to the first source and drain regions, respectively. This semiconductor device has a structure wherein the gate electrode is deeply buried in the substrate. Therefore, a short channel effect can be prevented.Type: GrantFiled: September 21, 1992Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiko Hieda, Fumio Horiguchi, Hiroshi Takato, Fujio Masuoka
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Patent number: 5371406Abstract: According to this invention, there is provided a semiconductor device including a TAB tape having through hole for an element, a plurality of leads integrally formed on the TAB tape, a semiconductor element connected to one end of each of the leads through a bump formed in the through hole for the element, a plurality of lead frames each connected to the other end of a corresponding one of the leads, and a mold resin sealed to cover the most part of the TAB tape, the leads, the semiconductor element, and the lead frames, wherein connection portions between the leads and the lead frames are linearly formed at equal pitches perpendicularly to an outer periphery of the semiconductor element opposite to the connection portions. Each of portions near positions where the leads are respectively connected to the lead frames is formed in a gull-wing shape.Type: GrantFiled: July 27, 1993Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Shinjiro Kojima, Seiichi Hirata
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Patent number: 5371703Abstract: Bipolar transistors are used to select memory cells of single-bit line output type. Bit lines are connected to the emitters of the selecting bipolar transistors, respectively. The collectors of the selecting bipolar transistors are connected to one another, thus forming a node. A potential which is higher than the ground potential and lower than a power-supply potential is applied to the gate of any one of the bipolar transistors which has been selected. This potential determines the maximum voltage of the bit lines. A current-sensing amplifier amplifies the difference between a reference potential and the potential of the collector node of the bipolar transistors, thus generating two output signals. A sense amplifier converts these output signals into a signal at a CMOS logic level, whereby the data stored in a selected memory cell is read out.Type: GrantFiled: July 21, 1993Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Junichi Miyamoto
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Patent number: 5371672Abstract: In a scintillation camera apparatus, a gamma-ray scattering signal component is removed from gamma-ray spectral energy distribution data. A scattering component removing method first detects an entire radiation emitted from a radioisotope having a specific energy level and injected into a biological body under medical examination to produce an entire radiation detecting signal. Then only first partial radiation from the radioisotope passing through a first energy range determined in relation to the specific energy level of the radioisotope is detected, thereby producing a first count value of the partial radiation. Partial second and third radiation from the radioisotope passing through second and third energy ranges positioned at both ends of the first energy range and also each having a width narrower than that of the first energy range are then detected, thereby producing second and third count values of the second and third partial radiation.Type: GrantFiled: February 26, 1992Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Nobutoku Motomura, Takashi Ichihara
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Patent number: 5370837Abstract: A high temperature heat-treating jig characterized by forming a tungsten layer or a tungsten alloy layer on the surface of a heat-resistant base to avoid discoloration and color shading during the heat treatment at a high temperature.Type: GrantFiled: January 12, 1994Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Masanori Kibata, Noboru Kitamori, Shigeki Kajima, Kazunori Yokosu, Mituo Kawai, Hideo Ishihara, Noriaki Yagi
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Patent number: 5370709Abstract: A suction plate is provided in a reaction chamber. In the central portion of the suction plate, there is formed a blowing port for blowing gas to a rear surface of the suction plate. In the blowing port, there are provide pipes for introducing carrier gas and reactant gas. Gas, which is introduced by these pipes, and the suction plate are heated by a lamp formed in the outside of the reaction chamber. If gas introduced by these pipes and reactant gas are blown from the blowing port to the rear of the suction plate in a state that a semiconductor substrate is close to the portion in the vicinity of the suction plate, the semiconductor substrate is sucked to the suction plate in a noncontact state and an epitaxial layer is formed on the semiconductor substrate in this state.Type: GrantFiled: July 17, 1991Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Norio Kobayashi
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Patent number: D353143Type: GrantFiled: December 22, 1992Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Seiji Namba