Patents Assigned to KABUSHIKI KAISHA TOSHIBA and
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Patent number: 5330934Abstract: A contact hole in a diffusion region is narrowed by a buffer layer formed at about the middle of an interlayer insulating film in its thickness direction. This buffer layer serves as effective alignment tolerances to the diffusion region and a contact electrode at the time of forming the contact hole. The structure having a wiring conductor filled in the contact hole and having the contact electrode formed on this wiring conductor can assure a highly reliable contact. Forming a buffer layer as a sidewall on this contact electrode and a first wiring layer formed on the same layer can assure an effective alignment tolerance to the first wiring layer at the time of forming a via hole. Filling a wiring conductor in the via hole can eliminate the need for any contact tolerance for a second wiring layer to be formed on this wiring conductor. Accordingly, the individual contact tolerances can be assured by self-alignment.Type: GrantFiled: June 16, 1993Date of Patent: July 19, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Shibata, Naoki Ikeda
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Heterojunction bipolar transistor with base electrode having Schottky barrier contact to the emitter
Patent number: 5331186Abstract: A high-cut-off frequency, high-speed HBT is obtained by suppressing the diffusion of impurities to the utmost by lowering a heat treatment temperature in the step subsequent to the formation of a high concentration base layer. A base electrode for a base layer is made of a metal or an intermetallic compound which extends the emitter layer to reach at least a part of the base layer. The metal or intermetallic compound forms Schottky barrier with an emitter layer having a wide forbidden width ,and ohmic contacts with the base layer with a narrow forbidden band. The barrier potential of the Schottky junction formed between the intermetallic compound or metal and the emitter layer is higher than the diffusion potential of a pn junction between the base layer and the emitter layer.Type: GrantFiled: March 5, 1992Date of Patent: July 19, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Kouhei Morizuka -
Patent number: 5331233Abstract: A plurality of differential amplifier circuits are supplied with respective potentials of a plurality of paired bit lines and subjects the potentials of the bit line pairs to the differential amplification. The plurality of differential amplifier circuits are connected to paired data lines. The paired data lines are connected at one end to a first clamping circuit for clamping the potential of the paired data lines. The first clamping circuit is connected to a common load circuit acting as a common load for the plurality of differential amplifier circuits. The paired data lines are connected at the other end to a second clamping circuit for reducing the amplitude of a voltage between the paired data lines.Type: GrantFiled: May 26, 1992Date of Patent: July 19, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Yukihiro Urakawa
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Patent number: 5331279Abstract: A magnetic resonance blood flow imaging method employs a field-echo technique and a gapless multi-slice acquisition technique in which a selective excitation pulse with a flip angle of less than 90 degrees is utilized and a pulse repetition time is set shorter than usual. Imaging data are acquired from multiple slices of a subject under examination while the multiple slices are shifted in sequence in position. A cross-sectional image is reconstructed for each of the multiple slices. Images obtained by performing subtractions on plural images for the same slice are gathered to thereby produce an image of blood vessels of the subject under examination which contain at least two blood vessels which run substantially in parallel and are opposite to each other in the direction of blood flow therein.Type: GrantFiled: August 19, 1993Date of Patent: July 19, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Masahiko Hatanaka
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Patent number: 5331647Abstract: A communication system comprising a communication path through which a message passes and, a plurality of communication apparatus, each apparatus includes a message transmission function to the communication path, and a read function for reading the message from the communication path. Each communication apparatus has a communication cumulative amount table so as to store the communication cumulative amount of messages transmitted by each communication apparatus as communication history data. The communication apparatus adds the latest communication cumulative amount in the communication cumulative amount table to a message which is transmitted to the communication path. The communication apparatus compares the stored communication cumulative amount table with the received communication cumulative amount. Thus, troubles of the communication subjects in the communication apparatus according to the result of the comparison can be detected.Type: GrantFiled: July 23, 1990Date of Patent: July 19, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Toshibumi Seki, Yasukuni Okataku, Shinsuke Tamura
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Patent number: 5330042Abstract: An escalator is arranged such that a first special step having a movable footplate capable of rising and falling is combined with a second special step adjacent to the upstream side of the first special step and having a projectable and retractable lift mechanism. The projectable and retractable lift mechanism supports the movable footplate of the first special step in part of a plurality of running steps provided endlessly in a line. When mounting a wheelchair, the movable footplate runs along the inclined path area with the movable footplate supported at the same height as the second special step by operating the lift mechanism in the horizontal path area of the travel path. The movable footplate ensures a rearward footplate dimension sufficient to carry the wheelchair.Type: GrantFiled: January 25, 1993Date of Patent: July 19, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Ogimura, Megumi Ookubo
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Patent number: 5329929Abstract: An ultrasonic diagnostic apparatus comprising unit for collecting echo signals by scanning a three-dimensional area of a subject with an ultrasonic beam, unit for making a three-dimensional bloodstream information based on the echo signals, unit for producing a plurality of projection images with different projecting directions based on the three-dimensional bloodstream information, and unit for displaying the plurality of projection images in specified sequence.Type: GrantFiled: August 17, 1992Date of Patent: July 19, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Sato, Akinami Ohhashi
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Patent number: 5331397Abstract: An inner lead bonding inspecting method comprises the steps of: irradiating an illumination light onto the planar surface of a bonding portion between an electrode bump provided on a semiconductor pellet and an inner lead, measuring the quantity of reflected light from the surface, and judging whether the bonding state of the inner lead bonding is good or bad on the basis of the measured result. According to another aspect, an inner lead bonding inspecting apparatus comprises any irradiation device for irradiating a light onto a planar surface of a bonding portion between an electrode bump provided on a semiconductor pellet and an inner lead; a light quantity measurement device for measuring the quantity of reflected light from the inner lead surface, and a judging device for comparing the measured quantity of reflected light with a reference light quantity, to judge the quality of the bonding state.Type: GrantFiled: November 9, 1992Date of Patent: July 19, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyuki Yamanaka, Mitsusada Shibasaka
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Patent number: 5331436Abstract: An encoder comprises a memory for storing a to-be-coded original image, outputting a to-be-coded image signal in response to a to-be-coded region designation signal for designating a to-be-coded region used as a to-be-coded block, and outputting a to-be-transformed image signal in response to a to-be-transformed region designation signal for designating a to-be-transformed region; a transforming circuit for subjecting the to-be-transformed image signal to a predetermined transformation in response to a transformation method designation signal, and outputting a transformed image signal; a deciding circuit for deciding an error of the transformed image signal with reference to the to-be-coded image signal, and a control circuit for outputting, as a code, information on at least the to-be-transformed region and the transformation method which reduce the error decided by the deciding circuit to a predetermined value or below.Type: GrantFiled: September 29, 1993Date of Patent: July 19, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Ida, Kenshi Dachiku
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Patent number: 5331508Abstract: A portable computer includes a housing and a keyboard unit mounted on the housing. A display unit is mounted on the housing to be movable between a closed position wherein the keyboard unit is covered by the display unit and a desired opened position wherein the keyboard is exposed. A latch mechanism for locking the display unit in the closed position is provided at the display unit. The mechanism includes a pair of latch hooks rockable between a latch position wherein each hook engages the housing and a release position wherein each hook is disengaged form the housing, and an interlocking member movable in interlock with the movement of the latch hooks. When a dial key attached to the display unit is turned on, the movement of the interlocking member is restricted by the key and the hooks are locked in the latch position.Type: GrantFiled: November 5, 1993Date of Patent: July 19, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Hosoi, Keizo Ohgami, Fumiaki Takeda
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Patent number: 5331679Abstract: A fuel spacer for a fuel assembly comprises a plurality of tubular ferrules each forming a fuel rod insertion passage, a belt-like support member for supporting the tubular ferrules bundled in a lattice arrangement and a spring member for axially supporting the fuel rods disposed in the ferrules. The adjoining ferrules are joined together horizontally, each of the ferrules has at least one end to which a plurality of cutout portions are formed circumferentially of the end portion and at least one flat portion is formed between adjoining petal portions at which the adjoining ferrules are spot welded. Each of the cutout portions and petal portions of the tubular ferrule has various shapes such as trapezoidal, rectangular, triangular, V or M shape. The cutout portions and petal portions may be formed at both axial ends of the tubular ferrule.Type: GrantFiled: December 8, 1992Date of Patent: July 19, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Koji Hirukawa
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Patent number: 5331144Abstract: A card reader-writer includes a body provided with a card inserting opening into which a card to which reading and writing of information can be made is inserted, magnetic heads arranged in the body to read and write information from and on the card, and a device for carrying the card which is inserted into the card inserting opening to the magnetic heads. The carrying device includes a card chucking unit for chucking the card and a carriage for moving the chucking unit along a certain passage. The position of the card chucked by the chucking unit is corrected by a card position adjusting or correcting unit.Type: GrantFiled: July 28, 1993Date of Patent: July 19, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Yasuo Shima, Makoto Ukai
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Patent number: 5331668Abstract: Disclosed is a communication control device in which a clock frequency for processing communication data is the same as or lower than the transfer speed of the communication data without requiring a complicated construction of the input-output portion to the network so as to make it possible to realize low power consumption and easy design and manufacture of the device.Type: GrantFiled: January 4, 1993Date of Patent: July 19, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Koichi Tanaka
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Patent number: 5331184Abstract: An insulated gate bipolar transistor having a low on-voltage and a low turn-off time is provided. P-type anode layer having a low impurity concentration, preferably 1.times.10.sup.16 to 1.times.10.sup.1 7/cm.sup.3, is provided on an N-type drain layer that includes a pair of P-type base regions each having an N.sup.+ -type source region. A plurality of P.sup.+ -type anode regions are formed in the P-type anode layer.Type: GrantFiled: August 11, 1992Date of Patent: July 19, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Masashi Kuwahara
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Patent number: 5331506Abstract: Disclosed herein is an electronic apparatus having a keyboard and a display unit and having a base unit made of a synthetic resin. The base unit comprises an upper case having a top wall and a peripheral wall, and a lower case having a bottom wall and a peripheral wall. The peripheral walls of the upper and lower cases are connected. A storage space is formed between the upper case and the lower case, for containing a battery pack. A loading port is formed in the sides of the upper and lower cases, communicating with said storage space. Though this port, the battery pack can be inserted into, and removed from, the storage space. A cover is connected to the base unit. It can move between a port-closing position where it closes the loading port and a second port-opening position where it opens the loading port. The cover has a top wall slidably mounted on the top wall of the upper case, and a lower wall slidably mounted on the bottom wall of the lower case.Type: GrantFiled: September 23, 1992Date of Patent: July 19, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Yuji Nakajima
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Patent number: 5329418Abstract: A circuit board packaging structure includes an array of rectangular pipe-shaped circuit modules with rows and columns. Each of the circuit modules has two opposite openings, inner wall surfaces which permit electric circuit components to be mounted thereon and have wiring patterns for electrical interconnection among the circuit components, and outer wall surfaces. Intermodule connectors are provided on the outer wall surfaces of the pipe-shaped circuit modules to permit electrical interconnection between each of the circuit modules and its associated circuit module. A cooling medium is forced to flow through each of the circuit modules in one direction, thereby directly or indirectly cooling the electric circuit components such as semiconductor integrated circuit devices mounted on the inner wall surfaces of the circuit modules.Type: GrantFiled: November 18, 1992Date of Patent: July 12, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Notoru Tanabe
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Patent number: 5329231Abstract: In a presaturation period, a radio-frequency (RF) pulse for selectively tilting only spins outside an imaging region is applied while a slice selective gradient field Gs is applied, and a spoiler gradient field Gsp for saturating transverse magnetization outside the imaging region is subsequently applied to selectively presaturate the spins outside the imaging region. In a high-speed imaging period after the presaturation period, a sequence TR constituted by an operation of applying a very short rectangular non-selective excitation pulse RF for tilting spins in a slice by a predetermined angle, an operation of applying phase encoding and readout gradient fields Gp and Gr (without applying the slice selective gradient field Gs), and an operation of acquiring an MR signal is performed many times while the amplitude of the phase encoding gradient field Gp is changed, thereby acquiring a one-slice MR signal.Type: GrantFiled: April 14, 1993Date of Patent: July 12, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Jun-ichi Hatta, Yoshio Machida
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Patent number: 5329154Abstract: An integrated circuit including a wafer having a GaAs substrate, an un-doped GaAs layer, and a GaAs active layer. This active layer may have an HEMT structure to improve its operation speed. Also, the substrate may a multi-layer structure to form a three dimensional capacitor. At least one mesa portion is formed on the substrate by removing a portion of the un-doped GaAs layer and GaAs active layer. A source electrode, for example, is formed on the mesa portion, and a ground electrode is formed on an exposed surface of the substrate. These electrodes are connected to each other by means of a wiring metal layer. As a result, the source electrode is easily grounded without using a long bonding wire.Type: GrantFiled: March 17, 1993Date of Patent: July 12, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Kishita, Toshikazu Fukuda, Yuji Minami
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Self turn-off insulated-gate power semiconductor device with injection-enhanced transistor structure
Patent number: 5329142Abstract: A self turn-off power semiconductor device includes a P type emitter layer, a high resistive N type base layer, a P type base layer and a MOS channel structure for injecting electrons into the N type base layer. A series of trench-like grooves are formed in the top surface of a substrate constituting the N type base layer at a constant interval. Insulated gate electrodes are buried in these grooves. The injection efficiency of electrons into the base layer is enhanced by locally controlling the flow of holes in the N type base layer. Controlling the flow of holes is achieved by specifically arranging the width of a hole-bypass path among the grooves, the trench width and the placement distance of the grooves, thereby causing the accumulation of carriers to increase in the base layer to decrease the on-resistance of the device.Type: GrantFiled: August 7, 1992Date of Patent: July 12, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuhiko Kitagawa, Ichiro Omura -
Patent number: D348887Type: GrantFiled: December 22, 1992Date of Patent: July 19, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Seiji Namba