Patents Assigned to Kabushiki Kaisha Toshiba
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Publication number: 20100158487Abstract: According to one embodiment, an authoring apparatus configured to generate writing data to be stored in an optical disc from a video content data, includes an indexing processor configured to generate face image indexing information includes face images extracted from the video content data and time stamp information representing a time point at which each extracted face image appears in the video content data, a setting module configured to set segments along with a time axis in the video content data, wherein a number of the segments is not larger than a number of chapters being able to be set in the writing data, and a generation module configured to generate menu screen data for displaying a menu screen displaying buttons on a display screen, the buttons on which face images are displayed respectively and for jumping to the segments in which the face images appearing.Type: ApplicationFiled: December 22, 2009Publication date: June 24, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Ken HAYASE
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Publication number: 20100156893Abstract: An information visualization device includes: a content specifier specifying a desired content item in a database; a first display information generator generating first display information by combining first meta-information items out of the meta-information items included in the desired content item; a second display information generator generating second display information by combining second meta-information items out of the meta-information items included in the desired content item; a display information placer generating an information CG model by placing the first and second display information on first and second surfaces of the CG model; a CG model attitude determiner determining an attitude of the information CG model in a virtual space so that the first or second surface is visible from a virtual viewpoint; and a CG model placer placing the information CG model with a determined attitude in the virtual space according to the position information.Type: ApplicationFiled: September 15, 2009Publication date: June 24, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Isao Mihara, Masahiro Sekine, Yasukazu Higuchi, Norihiro Nakamura, Yasunobu Yamauchi
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Publication number: 20100161913Abstract: In an IC card, an operating system manages the access order of each channel for each file using a channel management table. An application controls access to each file based on the access order managed in the channel management table. The channel management table stores, as an access order, an order that each logical channel has set a file in a current state. If current setting by a specific logical channel is canceled, a table updating function deletes the logical channel from the channel management table and moves up the access order of each logical channel next to the deleted logical channel.Type: ApplicationFiled: March 13, 2009Publication date: June 24, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: NORIO ISHIBASHI
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Publication number: 20100157310Abstract: An optical system including: a photon source; first directing elements configured to direct photons to follow a first path through the optical system; second directing elements configured to direct photons to follow a second path through the optical system, wherein the second path is the reverse of the first path, photons travelling through the first path having a different polarization to those travelling through the second path; and a mechanism varying the relative phase shift between photons following the first path and photons following the second path.Type: ApplicationFiled: May 16, 2008Publication date: June 24, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Anthony John Bennett, Richard Mark Stevenson, Andrew James Shields
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Publication number: 20100156024Abstract: An image forming apparatus is composed of a main body, an image forming portion provided in the main body to form an image on a sheet, a top receiving tray provided on a top of the main body to load the sheet on which the image is formed in the image forming portion so as to be visible from the top of the main body, a side receiving tray provided at a side of the main body and under the top receiving tray to load the sheet on which the image is formed in the image forming portion with a maximum sheet loading amount more than the top receiving tray, and a control unit to control to select one of the top receiving tray and the side receiving tray as a discharge destination for the sheet according to whether or not a number of the output sheets outputted from the image forming portion exceeds a prescribed threshold value.Type: ApplicationFiled: August 11, 2009Publication date: June 24, 2010Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA TEC KABUSHIKI KAISHAInventor: Norio TANAKA
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Publication number: 20100157648Abstract: A semiconductor integrated circuit device includes a first block, a second block, and a control section. The first block includes a first fuse, a first switching configured to write data to the first fuse, a first holding portion capable of holding a first instruction, and a first instruction portion configured to turn on the first switching when a second instruction is given thereto with the first instruction. The second block includes a second fuse, a second switching configured to write data to the second fuse, a second holding portion capable of holding the first instruction, and a second instruction portion configured to turn on the second switching when the second instruction is given thereto with the first instruction. The control section issues the second instruction at a point in time when the first instruction is held in the first and second holding portions.Type: ApplicationFiled: September 8, 2009Publication date: June 24, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Tomohiro Kobayashi
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Publication number: 20100161885Abstract: A semiconductor storage device includes a first storage unit having a plurality of first blocks as data write regions; an instructing unit that issues a write instruction of writing data into the first blocks; a converting unit that converts an external address of input data to a memory position in the first block with reference to a conversion table in which external addresses of the data are associated with the memory positions of the data in the first blocks; and a judging unit that judges whether any of the first blocks store valid data associated with the external address based on the memory positions of the input data, wherein the instructing unit issues the write instruction of writing the data into the first block in which the valid data is not stored, when any of the first blocks does not store the valid data.Type: ApplicationFiled: September 8, 2009Publication date: June 24, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Shinichi KANNO, Shigehiro Asano, Kazuya Kitsunai, Hirokuni Yano, Toshikatsu Hida
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Publication number: 20100161659Abstract: An information supplying server includes a retrieval request receiver (101) for receiving a query containing a keyword, a retriever (102) for transmitting a received query to a retrieval server identified by a retrieval destination identifier associated with a superordinate concept of received keyword in retrieval destination data, and receiving a retrieved data from the retrieval server, a narrowing word determiner (103) for determining a narrowing word in accordance with a priority determined from a provisional priority set to a narrowing word candidate as a candidate of narrowing word for use to narrow down information from retrieved data, and a degree of relevancy set to a superordinate concept of narrowing word candidate and a superordinate concept of the keyword, and a supply data transmitter (107) configured to transmit to the client terminal a supply data as a synthesis of the retrieved data with a new query having a determined narrowing word combined with the received query.Type: ApplicationFiled: December 16, 2009Publication date: June 24, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Isao TAKEYASU
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Publication number: 20100156508Abstract: According to one embodiment, an electronic device includes a housing, an operation area, at least one display, an input detector, a light source device, and a controller. The operation area is provided on an outer surface of the housing. The display is located in the operation area, and includes a first indicator and a second indicator made of a light transmissive material. The first indicator corresponds to a design that indicates operation content, while the second indicator is located in a position not covered by an operation tool with which operation is performed on the first indicator and indicates operation state. The input detector faces the operation area in the housing and detects electrostatic capacitance in the operation area. The light source device emits light to the display in the operation area. The controller controls the light source device based on a variation in electrostatic capacitance detected by the input detector to turn on or off at least the second indicator.Type: ApplicationFiled: September 9, 2009Publication date: June 24, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Shinsuke Yato
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Publication number: 20100159617Abstract: A semiconductor-device manufacturing method includes steps of performing a sidewall fabrication thereby forming a first pattern structure; measuring an amount of displacement of line portions of the first pattern structure; correcting an overlay specification for an overlay of the first pattern structure and a second pattern structure dynamically based on the amount of displacement; and determining whether an error in the overlay of the first pattern structure and the second pattern structure meets the corrected overlay specification.Type: ApplicationFiled: July 31, 2009Publication date: June 24, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yuji KOBAYASHI
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Publication number: 20100161881Abstract: A memory system (10) is disclosed, which comprises a flash-EEPROM nonvolatile memory (11) having a plurality of memory cells that have floating gates and in which data items are electrically erasable and writable, a cache memory (13) that temporarily stores data of the flash-EEPROM nonvolatile memory (11), a control circuit (12, 14) that controls the flash-EEPROM nonvolatile memory (11) and the cache memory (13), and an interface circuit (16) that communicates with a host, in which the control circuit functions to read data from a desired target area to-be-determined of the flash-EEPROM nonvolatile memory and detect an erased area to determine a written area/unwritten area by using as a determination condition whether or not a count number of data “0” of the read data has reached a preset criterion count number.Type: ApplicationFiled: March 3, 2009Publication date: June 24, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Yasushi Nagadomi, Daisaburo Takashima, Kosuke Hatsuda
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Publication number: 20100157693Abstract: A semiconductor memory device comprises a memory cell array including a plurality of word lines, a plurality of bit lines intersecting the plurality of word lines, and a plurality of binary-data holding memory cells arranged at the intersections of the word lines and the bit lines; and a control unit operative to change in the storage capacity of the memory cell array and change in the address space required for access to the memory cell based on a control signal.Type: ApplicationFiled: November 6, 2009Publication date: June 24, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takayuki Iwai, Takayuki Miyazaki, Mariko Iizuka
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Publication number: 20100158755Abstract: A method for dispensing a sample solution and a reagent into a container in a chemical analyser includes a first step of dispensing a reagent into a container, a second step of dispensing a sample solution into the container after the first step, and a third step of dispensing the reagent into the container after the second step. A dilution cup includes an inner face where a diameter of a horizontal section increases on at least one position from a bottom to a top, an opening portion surrounding an opening, where a sample solution is dispensed, located on or near the top, a reagent aperture portion surrounding an aperture where a reagent is dispensed such that the sample solution and the reagent create an upswing spiral flow, and a drain aperture portion surrounding a drain aperture, where a mixed solution of the sample solution and the reagent is discharged, located on or near the bottom.Type: ApplicationFiled: March 3, 2010Publication date: June 24, 2010Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MEDICAL SYSTEMS CORPORATIONInventors: Hitoshi Shibutani, Naoto Sato
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Publication number: 20100161696Abstract: A random number generator which includes a bus including a plurality of bus lines configured to send and receive a signal between a circuit and another circuit, a calibration unit configured to dynamically adjust a reception condition of the signal, and a random number generating unit configured to generate a random number based on adjustment information of the calibration unit.Type: ApplicationFiled: November 6, 2009Publication date: June 24, 2010Applicant: Kabushiki Kaisha ToshibaInventor: Akihiro Matsui
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Publication number: 20100155365Abstract: According to one embodiment, when forming first, second, and third stampers by transferring three-dimensional patterns of a master, a height adjusting layer having a film thickness greater on the upper surface of a projection than on the bottom surface of a recess is formed between the second stamper and a second release layer, and the surface of the third stamper is etched with an acidic solution having a pH of less than 3.Type: ApplicationFiled: December 17, 2009Publication date: June 24, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takuya SHIMADA, Shinobu SUGIMURA, Yoshiyuki KAMATA, Masatoshi SAKURAI
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Publication number: 20100157656Abstract: A resistance change memory of an aspect of the present invention including memory cells including resistance change memory element, word lines connected to the memory cells, a row decoder which activates the word lines, redundant cells used instead of defective cells, a redundant word line connected to redundant cells, a redundant row decoder which activates the redundant word line, a control circuit in which defect address information indicating the word line connected to the defective cell is stored and which remedies the defective cell, and regions provided in a memory cell array and a redundant cell array and identified based on column address information, wherein the control circuit replaces a part of the word line connected to the defective cell with a part of the redundant word line in accordance with each of the regions, and allows the redundant row decoder to activate the replaced redundant word line.Type: ApplicationFiled: September 21, 2009Publication date: June 24, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kenji Tsuchida
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Publication number: 20100162127Abstract: According to one embodiment, an information processing system includes at least one remote apparatus and a local terminal connected to the at least one remote apparatus via a network. The at least one remote apparatus transmits a screen image on which objects are drawn, and drawing region data which indicates a region on the screen image where each of the objects is drawn. The local terminal receives the screen image and the drawing region data from the at least one remote apparatus, extracts images corresponding to the objects from the received screen image based on the received drawing region data, and displays the extracted images of the objects on a display screen.Type: ApplicationFiled: September 11, 2009Publication date: June 24, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Satoshi Uchino
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Publication number: 20100158481Abstract: According to the invention, a video reproducing apparatus includes: a reading module configured to read out video information and caption information, the video information including control information; a video processing module configured to generate a display image to be displayed on a screen, the display image having an image corresponding to the control information; a caption processing module configured to generate a subpicture based on the caption information, the subpicture including a caption image for a caption and a mask image for masking the image corresponding to the control information when the subpicture is superimposed on the display image; a video synthesizing module configured to generate an overlapped display image by superimposing the subpicture; and a video signal outputting module configured to output the overlapped display image to a control signal extracting apparatus that extracts a control signal from the masked image corresponding to the control information.Type: ApplicationFiled: June 29, 2009Publication date: June 24, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yuki Kaneko, Shinji Kuno
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Patent number: 7740486Abstract: An electronic device, comprising an improved printed circuit board connection for connecting a first printed circuit board to a second printed circuit board in a manner that permits physical engagement at a different position than the electrical engagement, and a method for making the improved printed circuit board connection with precision in alignment. In one embodiment, the first printed circuit board includes an end portion configured to engage with a member of a connector on the second printed circuit board. The end portion and the member engage along concave portions of the end portion and convex portions of the member. When engaged, the end portion and the member align wires of the first printed circuit board with terminals of the connector.Type: GrantFiled: May 14, 2008Date of Patent: June 22, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Nagahisa Watanabe
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Patent number: 7740939Abstract: An insulating magnetic metal particle includes a magnetic metal particle containing at least one metal selected from the group consisting of Co, Fe, and Ni and having a diameter of 5 to 500 nm, a first inorganic insulating layer made of an oxide that covers the surface of the magnetic metal particle, and a second inorganic insulating layer made of an oxide that produces a eutectic crystal by reacting together with the first inorganic insulating layer at the time of heating them, the second inorganic insulating layer being coated on the first inorganic insulating layer. A thickness ratio of the second inorganic insulating layer with respect to the first inorganic insulating layer is set so that the first inorganic insulating layer remains on the surface of the magnetic metal particle after producing the eutectic crystal.Type: GrantFiled: July 23, 2007Date of Patent: June 22, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Kouichi Harada, Tomohiro Suetsuna, Seiichi Suenaga, Maki Yonetsu