Patents Assigned to Kabushiki Kaisha Toshiba
  • Publication number: 20240405382
    Abstract: According to one embodiment, a secondary battery includes an outer container with a lid, an electrode body stored in the outer container and including an electrode group, a positive electrode current collecting tab group and a negative electrode current collecting tab group, output terminals on the lid, a positive electrode lead, and a negative electrode lead. A second joint portion of the electrode leads has a first joint surface and a second joint surface opposing each other. A part of current collector tab groups of the same polarity is joined to the first joint surface, and another part of the group of current collector tabs of the same polarity is joined to the second joint surface and opposing the part of the current collector tab groups across the second joint portion.
    Type: Application
    Filed: August 15, 2024
    Publication date: December 5, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takuma YANO, Shusuke MORITA, Yoshiaki ARAKI
  • Publication number: 20240401949
    Abstract: According to one embodiment, a sensor includes an element section. The element section includes a base, a first fixed portion, a first intermediate connect portion, a first intermediate movable member, a first connect portion, a first movable member, and a first fixed electrode. The first fixed portion is fixed to the base. The first intermediate connect portion is supported by the first fixed portion. The first intermediate movable member is connected to the first intermediate connect portion. The first connect portion is connected to the first intermediate movable member. The first movable member is supported by the first connect portion. The first movable member includes a first movable electrode. The first fixed electrode is fixed to the base and faces the first movable electrode.
    Type: Application
    Filed: January 26, 2024
    Publication date: December 5, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideaki MURASE, Yasushi TOMIZAWA, Daiki ONO, Fumito MIYAZAKI, Kengo UCHIDA, Kei MASUNISHI, Etsuji OGAWA, Jumpei OGAWA, Fumitaka ISHIBASHI
  • Patent number: 12159629
    Abstract: According to one embodiment, an information processing apparatus includes a processor. The processor generates a template, regarding a recording data sheet including a plurality of items, for one or more of the items that can be specified, with reference to an input order of input target items selected from the items. The processor performs a speech recognition on an utterance of a user and generate a speech recognition result. The processor determines an input target range relating to one more items specified by the utterance of the user among the items based on the template and the speech recognition result.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: December 3, 2024
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nayuko Watanabe, Toshiaki Nakasu
  • Patent number: 12159932
    Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, first, second, and third semiconductor layers, and a first insulating member. The first semiconductor layer includes first, second, third, fourth, and fifth partial regions. The third partial region is between the first and second partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The first electrode includes a first electrode portion. The second semiconductor layer includes first and second semiconductor portions. The third semiconductor layer includes first and second semiconductor regions. The second semiconductor region is electrically connected to the first semiconductor region and the first electrode portion. The first insulating member includes a first insulating portion. The first insulating portion is provided between the third partial region and the third electrode.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: December 3, 2024
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Jumpei Tajima, Toshiki Hikosaka, Shinya Nunoue
  • Patent number: 12158406
    Abstract: A binding capacity evaluation apparatus includes a first solution tank into which a first solution is input, the first solution including a hydrophobic substance and a hydrophilic substance; a second solution tank into which a second solution is input, the second solution including water as a major component; a light irradiation device irradiating light on a third solution including a mixture of the first and second solutions; a light-receiving device receiving light passing through the third solution; and a light transmittance measuring device measuring light transmittance by using an intensity of the light received by the light-receiving device. The apparatus uses the light transmittance to detect when the hydrophobic substance becomes supersaturated in the second solution.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: December 3, 2024
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Sugizaki
  • Patent number: 12158744
    Abstract: According to one embodiment, an analysis device performs an analysis related to a plurality of tasks of a manufacturing process. The analysis device receives an image when each of the plurality of tasks is performed. The analysis device receives the images from an imaging device acquiring the images. The analysis device receives a detection signal from a tool used in at least one of the plurality of tasks. The detection signal is detected by the tool. The analysis device refers to end determination data for determining an end of each of the plurality of tasks. The analysis device determines the end of each of the plurality of tasks based on the images, the detection signal, and the end determination data.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: December 3, 2024
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takanori Yoshii, Hiroaki Nakamura, Takehiro Kato, Makoto Tsuji, Yasuo Namioka
  • Patent number: 12160959
    Abstract: A bonded body includes a ceramic substrate and a copper plate, in which the copper plate is bonded to the ceramic substrate via a bonding layer, the copper plate includes a surface perpendicular to a direction in which the ceramic substrate and the copper plate are bonded, and a number percentage of copper crystal grains having major diameters greater than 400 ?m in three 5 mm×5 mm regions included in the surface is not less than 0% and not more than 5%. The bonding temperature is favorably not more than 800° C. The number percentage of the copper crystal grains having major diameters greater than 400 ?m is favorably not more than 1%.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: December 3, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Maki Yonetsu, Seiichi Suenaga, Sachiko Fujisawa, Takashi Sano
  • Patent number: 12157029
    Abstract: According to an embodiment, a process apparatus performs processing on a byproduct generated in a reaction of a raw material including silicon and a halogen element or in a reaction between a raw material including silicon and a raw material including a halogen element. The apparatus includes a process liquid tank, a processing tank, a supplier and an exhauster. A process target member including the byproduct is introduced into the processing tank. The supplier supplies the process liquid from the process liquid tank to the processing tank and performs processing on the byproduct with the supplied process liquid. The exhauster exhausts a gas generated by reaction between the process liquid and the byproduct from the processing tank.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: December 3, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, Kioxia Corporation, TOHOKU UNIVERSITY
    Inventors: Kenya Uchida, Hiroyuki Fukui, Ikuo Uematsu, Takeaki Iwamoto, Eunsang Kwon
  • Patent number: 12159954
    Abstract: A light detector according to one embodiment includes a substrate, a plurality of avalanche photodiodes, a well region, and a microlens array. The plurality of avalanche photodiodes are provided above the substrate. Each of the avalanche photodiodes is surrounded by a trench portion among a plurality of trench portions. The well region is provided between the trench portions that are adjacent to each other. The well region includes at least one of a transistor and a diode. The microlens array is provided to cover the avalanche photodiodes.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: December 3, 2024
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Kokubun, Nobu Matsumoto, Mitsuhiro Sengoku
  • Patent number: 12159728
    Abstract: A method of producing a light water reactor fuel assembly may include: setting conditions at least concerning an operation cycle period and burnup; setting an initial enrichment of enriched uranium; calculating excess reactivity of a light water reactor core where light water reactor fuel assemblies including the enriched uranium are burned until an end stage of a final operation cycle; determining whether a condition where excess reactivity at an end of a first operation cycle in the burnup calculation step is close to a predetermined positive value is true or not; and returning to the setting of the initial enrichment, when it is determined at the determining that the situation is not true, or deciding an enrichment of the enriched uranium when it is determined that the situation is true.
    Type: Grant
    Filed: July 7, 2023
    Date of Patent: December 3, 2024
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouji Hiraiwa, Rei Kimura, Shungo Sakurai, Rie Aizawa, Goro Yanase, Shinichiro Kawamura
  • Patent number: 12161054
    Abstract: An oxide superconductor of an embodiment includes an oxide superconducting layer including a first superconducting region containing barium, copper, and a first rare earth element, having a continuous perovskite structure, and extending in a first direction, a second superconducting region containing barium, copper, and a second rare earth element, having a continuous perovskite structure, and extending in the first direction, and a non-superconducting region disposed between the first and the second superconducting region, containing praseodymium, barium, copper, and a third rare earth element, a ratio of the number of atoms of the praseodymium to a sum of the number of atoms of the third rare earth element and the number of atoms of the praseodymium which is 20% or more, having a continuous perovskite structure continuous with the perovskite structure of the first superconducting region and the perovskite structure of the second superconducting region, and extending in the first direction.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: December 3, 2024
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Araki, Hirotaka Ishii
  • Patent number: 12159757
    Abstract: According to one embodiment, provided is a method of manufacturing a composite electrode including a substrate having a belt shape and an insulating fiber film disposed on the substrate. The method includes applying a primer solution onto the substrate, and ejecting an electrified material liquid in a direction parallel to principal surfaces of the substrate intersecting with side surfaces of the substrate to deposit the electrified material liquid onto the substrate to form the insulating fiber film on the principal surfaces of the substrate.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: December 3, 2024
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kenichi Ooshiro
  • Patent number: 12159927
    Abstract: A semiconductor device includes a semiconductor layer having a first plane and a second plane; an emitter electrode on a side of the first plane; at least one collector electrode on a side of the second plane; a first gate electrode on the side of the first plane; at least one second gate electrode on the side of the second plane; a drift region of a first conductivity-type in the semiconductor layer; a collector region of a second conductivity-type in the semiconductor layer; and a first conductivity-type region of the first conductivity-type provided between a part of the collector region and the second plane, wherein the semiconductor device has a first effective gate distance and a second effective gate distance different from the first effective gate distance.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: December 3, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yoko Iwakaji, Tomoko Matsudai, Takeshi Suwa
  • Publication number: 20240391110
    Abstract: According to an embodiment, a handling system includes a holder and controller. The holder holds an object. The controller controls the holder. The controller acquires information about physical properties of the object. The controller generates a holding plan for holding the object by the holder on the basis of the physical properties. The holding plan includes information of a holding region of the object in which the object is held by the holder. The controller causes the holder to hold the object on the basis of the holding plan.
    Type: Application
    Filed: August 6, 2024
    Publication date: November 28, 2024
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Haruna ETO, Akihito OGAWA, Seiji TOKURA, Kazuma KOMODA
  • Publication number: 20240396391
    Abstract: According to an embodiment, an interior permanent-magnet rotor includes: a rotor shaft; permanent magnets at least one of which is provided at each magnetic pole; and a rotor core attached to a radially outer side of the rotor shaft and formed with permanent magnet housing holes for storing the permanent magnets, respectively. Each of the permanent magnet housing holes has an opening part in communication with a radially outer side of the rotor core and sandwiched between an opening-part circumferentially inner-side tip and an opening-part circumferentially outer-side tip of the rotor core. The rotor core has a relaxing part formed with shapes of the opening-part circumferentially inner-side tip and the opening-part circumferentially outer-side tip.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION
    Inventors: Masakatsu MATSUBARA, Daisuke Mori, Naoya Sasaki, Masaru Kano
  • Publication number: 20240396061
    Abstract: A hydride-ion-conducting device includes a first layer, a first protective layer, a second protective layer and a conductive layer. The first layer includes a hydride-ion-conducting material. The first layer includes a protrusion protruding in an upward direction. The first protective layer is located on the first layer. The first protective layer includes an upper surface extending in a first direction crossing the upward direction. The upper surface of the first protective layer is aligned with an upper end of the protrusion in the first direction. The second protective layer is located on the first layer and on the first protective layer. The conductive layer is located on the second protective layer.
    Type: Application
    Filed: March 11, 2024
    Publication date: November 28, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tomomichi NAKA
  • Publication number: 20240393131
    Abstract: According to one embodiment, an information processing apparatus includes a processor. The processor is configured to acquire first received power measured by a moving vehicle at a first position of the moving vehicle which receives a first signal which is a radio wave, and acquire a coefficient which associates the acquired first received power with a radio wave shielding state in an environment including a second position different from the first position.
    Type: Application
    Filed: February 21, 2024
    Publication date: November 28, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daisuke UCHIDA, Tatsuma HIRANO, Satoshi TAKAYA, Tomoya TANDAI
  • Publication number: 20240394596
    Abstract: According to one embodiment, an information processing device includes one or more processors. The one or more processors are configured to: detect whether input waveform data is in a first state by using a detection model; acquire a plurality of pieces of second state waveform data in a second state detected in advance by using the detection model when detected to be in the first state; learn a classification model for classifying whether waveform data is in the first state or the second state, by using first state waveform data detected to be in the first state and the plurality of pieces of second state waveform data as learning data, to generate one or more partial waveform patterns serving as a basis for indicating that the first state waveform data is in the first state; and output the generated partial waveform pattern.
    Type: Application
    Filed: February 27, 2024
    Publication date: November 28, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihiro YAMAGUCHI, Ken UENO, Ryusei SHINGAKI
  • Publication number: 20240390935
    Abstract: According to an embodiment, a winding apparatus includes a winding core and an air flow controller. The winding core winds a belt-shaped structure comprising a substrate and an edge-coating part that covers an edge of a substrate in a width direction, the edge-coating part being coated with a material liquid on a surface of the substrate. The air flow controller has a nozzle that performs at least either ejection or suction of a gas, and adjusts an air flow in the vicinity of the edge-coating part of the film of the belt-shaped structure, which is wound by a winding core.
    Type: Application
    Filed: August 2, 2024
    Publication date: November 28, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shiori HIROSE, Masahiro TOKOH, Kenichi OOSHIRO
  • Publication number: 20240395543
    Abstract: According to one embodiment, a wafer includes a silicon substrate, a first layer, and a plurality of structures. The first layer includes aluminum and nitrogen. The plurality of structures are provided between a part of the silicon substrate and a part of the first layer in a first direction from the silicon substrate to the first layer. The plurality of structures includes a first element and silicon. The first element includes at least one selected from the group consisting of Ni, Cu, Cr, Mn, Fe and Co. Another part of the first layer is in contact with another part of the silicon substrate.
    Type: Application
    Filed: February 23, 2024
    Publication date: November 28, 2024
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hisashi YOSHIDA, Ryoma KANEKO, Hajime NAGO, Toshiki HIKOSAKA