Patents Assigned to Kabushiki Kaishi Toshiba
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Publication number: 20070061679Abstract: In a coding system wherein an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part 212 for coding an input multiplexed code string 201 to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part 213 for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string 201, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string 201 to assemble an output code string 205.Type: ApplicationFiled: October 23, 2006Publication date: March 15, 2007Applicant: Kabushiki Kaishi ToshibaInventors: Yoshihiro Kikuchi, Toshiaki Watanabe, Kenshi Dachiku, Takeshi Chujoh, Takeshi Nagai, Toshiaki Watanabe, Kenshi Dachiku, Takeshi Chujoh, Takeshi Nagai
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Patent number: 7035433Abstract: An image recognition apparatus has an image capture section for capturing a range image, an image deformation section for deforming the range image captured by the image capture section, and a recognition section for recognizing the presence/absence of three-dimensional motion of an object by comparing the deformed image obtained by the image deformation section, and a new range image captured by the image capture section.Type: GrantFiled: December 23, 1999Date of Patent: April 25, 2006Assignee: Kabushiki Kaishi ToshibaInventors: Isao Mihara, Yasunobu Yamauchi, Akira Morishita, Miwako Doi
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Patent number: 6907186Abstract: An information storage medium capable of recording and playing back still picture information is provided with a first information unit having one still picture information, and a first group unit which is composed of a set of first information units, and has a plurality of pieces of still picture information having different contents. Information is recorded in the first group unit.Type: GrantFiled: February 19, 2002Date of Patent: June 14, 2005Assignee: Kabushiki Kaishi ToshibaInventors: Hideo Ando, Shinichi Kikuchi, Kazuhiko Taira, Yuji Ito
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Patent number: 6816413Abstract: A nonvolatile semiconductor memory includes a plurality of nonvolatile memory cells each having a gate, a drain and a source to hold data corresponding to a threshold voltage level. The memory further includes a reference current generation circuit which generates a reference current, the reference current generation circuit including at least one reference cell and an amplification circuit which amplifies a current flowing through the reference cell, and a ratio of an amplification factor of current in a program verify mode to an amplification factor of current in a data read mode is larger than 1, and a sense amplifier which compares the reference current with a current flowing through selected ones of the nonvolatile memory cells and reads data held in the selected ones of the nonvolatile memory cells.Type: GrantFiled: July 15, 2003Date of Patent: November 9, 2004Assignee: Kabushiki Kaishi ToshibaInventor: Toru Tanzawa
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Publication number: 20040044737Abstract: A planning means generates a plan to be executed by agents on a node. In the case where the plan generated uses an uncertain knowledge required to be processed in other nodes, a judging means judges the communication line connecting the node and a network is low or high in reliability. In the case where the reliability of the communication line is low, an agent management unit moves the agent for executing the plan to another node for processing the uncertain knowledge. In the case where the reliability of the communication line is high, on the other hand,. a cooperation protocol realization means requests an agent on another node to process the uncertain knowledge. An agent execution means executes the plan generated.Type: ApplicationFiled: March 21, 2003Publication date: March 4, 2004Applicant: KABUSHIKI KAISHI TOSHIBAInventors: Masanori Hattori, Yasuo Nagai, Yutaka Irie, Akihiko Ohsuga, Shinichi Honiden
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Publication number: 20040032895Abstract: A monolithic two-wavelength semiconductor laser device includes a front end face film 19 on a resonator front end face 18, and a high-reflectivity end face film 22 as a multilayered film on a resonator rear end face 21. The front end face film 19 is formed using a low-refractive-index material, and the film thickness is so set that the reflectivity is 20%. The high-reflectivity end face film 22 is formed by alternately stacking thin films of low- and high-refractive-index materials, and the film thickness is so set that the reflectivity is 80%. The film thickness of each of these two end face films is calculated by an optical length d=(1/4+j)×&lgr;m by using a mean value &lgr;m=(&lgr;1+&lgr;2)/2 of the oscillation wavelengths of the two semiconductor laser diodes.Type: ApplicationFiled: August 14, 2003Publication date: February 19, 2004Applicant: KABUSHIKI KAISHI TOSHIBAInventors: Makoto Okada, Koichi Gen-Ei
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Publication number: 20040019627Abstract: A planning means generates a plan to be executed by agents on a node. In the case where the plan generated uses an uncertain knowledge required to be processed in other nodes, a judging means judges the communication line connecting the node and a network is low or high in reliability. In the case where the reliability of the communication line is low, an agent management unit moves the agent for executing the plan to another node for processing the uncertain knowledge. In the case where the reliability of the communication line is high, on the other hand, a cooperation protocol realization means requests an agent on another node to process the uncertain knowledge. An agent execution means executes the plan generated.Type: ApplicationFiled: March 21, 2003Publication date: January 29, 2004Applicant: KABUSHIKI KAISHI TOSHIBAInventors: Masanori Hattori, Yasuo Nagai, Yutaka Irie, Akihiko Ohsuga, Shinichi Honiden
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Publication number: 20040003047Abstract: A planning means generates a plan to be executed by agents on a node. In the case where the plan generated uses an uncertain knowledge required to be processed in other nodes, a judging means judges the communication line connecting the node and a network is low or high in reliability. In the case where the reliability of the communication line is low, an agent management unit moves the agent for executing the plan to another node for processing the uncertain knowledge. In the case where the reliability of the communication line is high, on the other hand, a cooperation protocol realization means requests an agent on another node to process the uncertain knowledge. An agent execution means executes the plan generated.Type: ApplicationFiled: March 21, 2003Publication date: January 1, 2004Applicant: KABUSHIKI KAISHI TOSHIBAInventors: Masanori Hattori, Yasuo Nagai, Yutaka Irie, Akihiko Ohsuga, Shinichi Honiden
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Publication number: 20030177433Abstract: In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detect-ion are solved. There is provided a coding part 212 for coding an input multiplexed code string 201 to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part 213 for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string 201, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string 201 to assemble an output code string 205.Type: ApplicationFiled: April 9, 2003Publication date: September 18, 2003Applicant: Kabushiki Kaishi ToshibaInventors: Yoshihiro Kikuchi, Toshiaki Watanabe, Kenshi Dachiku, Takeshi Chujoh, Takeshi Nagai
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Publication number: 20020190368Abstract: A semiconductor laminated module comprises a plurality of unit packages in which semiconductor chips are bonded to base substrates with a first adhesive, a second adhesive to form a laminated body by bonding the plurality of unit packages to each other, a third adhesive formed to cover an upper surface of the semiconductor chips and having substantially the same thermal expansion coefficient as that of the first adhesive, and an uppermost substrate bonded to uppermost one of the unit packages with the second adhesive.Type: ApplicationFiled: June 18, 2002Publication date: December 19, 2002Applicant: KABUSHIKI KAISHI TOSHIBAInventors: Hiroshi Shimoe, Naohisa Okumura, Takashi Imoto, Ryuji Hosokawa
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Publication number: 20020090206Abstract: Data is recorded in a data area of a disk in a hierarchical structure of program chains, programs, cells and packs, each pack is constructed by a pack header for identifying the pack and a packet having a data stream recorded therein, the packet has a packet header having a stream ID indicating at least a private stream and a sub-stream ID indicating the classification of the private stream described therein, and the classification indicates packet data of Dolby AC3 audio data, packet data of linear audio data, packet data of sub-picture data, or packet data of computer data.Type: ApplicationFiled: February 20, 2001Publication date: July 11, 2002Applicant: Kabushiki Kaishi ToshibaInventors: Shinichi Kikuchi, Kazuhiko Taira, Tomoaki Kurano, Hideki Mimura
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Publication number: 20010012390Abstract: Pattern inspection equipment has at least a measured data generation unit for generating measured data from patterns that have been delineated on a sample according to design data, a reference data generation unit for generating reference data used to inspect the patterns from gradational data expressed in multiple gradation levels, and a fault decision circuit for comparing the measured data with the reference data. The reference data generation unit has a multi-valued pattern development circuit for developing the design data into the gradational data and a fine adjustment circuit for finely shifting the positions or adjusting the curvatures of pattern edges in the pattern constructed with the gradational data. The fine adjustment of the pattern edges is necessary to cope with slightly displaced edges and rounded corners of the actual patterns on the sample.Type: ApplicationFiled: July 27, 1998Publication date: August 9, 2001Applicant: KABUSHIKI KAISHI TOSHIBAInventor: TOSHIYUKI WATANABE
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Patent number: 6259493Abstract: Not only a signal line (27a) but also an adjacent signal line (27b) partly oppose a reflection pixel electrode (50a) through an insulating film to be capacitively coupled to the electrode. The area of that portion (27a1) of the signal line (27a) which opposes the reflection pixel electrode (50a) is almost equal to that of that portion (27b2) of the signal line (27b) which oppose the pixel electrode (50a). Therefore, the influence of the signal potential of the signal line (27a) on the reflection pixel electrode (50a) through capacitive coupling is nearly equal to that of the signal potential of the signal line (27b) on the reflection pixel electrode (50a) through capacitive coupling. Luminance differences between adjacent pixels (50a and 50b; 50b and 50c, . . . ) are reduced, thereby preventing crosstalk.Type: GrantFiled: June 4, 1999Date of Patent: July 10, 2001Assignee: Kabushiki Kaishi ToshibaInventors: Takashi Nakamura, Yasuyuki Hanazawa, Kohei Nagayama
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Publication number: 20010001507Abstract: In the substrate for a semiconductor device of the present invention, a second substrate having an opening portion is adhered on a first flat substrate. The opening portion makes the surface of the first substrate exposed and contains a semiconductor chip. Chip connection terminals to be connected to the semiconductor chip are provided on the second substrate. External connection terminals are provided on the back surface of the first substrate. The chip connection terminals and the external connection terminals are connected with each other by a wiring pattern passing through through-holes formed and penetrating both the first and second substrate.Type: ApplicationFiled: May 27, 1997Publication date: May 24, 2001Applicant: Kabushiki Kaishi ToshibaInventors: MASATOSHI FUKUDA, JUN OHMORI
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Patent number: 6108563Abstract: A communication setting pattern indicating whether or not the mobile stations located in the radio zone are permitted to communicate is set for each radio zone in a communication setting memory. In a case where a call request related to a mobile station located in the service area has been made, a CPU carries out the call process corresponding to the call request only when the communication pattern permits communication in the radio zone where the mobile station related to the call request is located. When the communication setting pattern stored in the communication setting memory has been changed, the CPU disconnects the call related to the mobile station in a case where a busy mobile station is located in the radio zone where the changed communication permit/inhibit information inhibits communication.Type: GrantFiled: March 21, 1997Date of Patent: August 22, 2000Assignee: Kabushiki Kaishi ToshibaInventor: Shinichi Shishino
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Patent number: 6055188Abstract: A memory cell array includes first and second memory cell groups which are simultaneously selected at the time of erasing. A first bit line is connected to the first memory cell group and a second bit line is connected to the second memory cell group. The first and second bit lines are commonly connected to a data circuit having a latch circuit. First data read from the first memory cell group at the time of erase verify read for the first memory cell group is input to the data circuit and second data read from the second memory cell group at the time of erase verify read for the second memory cell group is input to the data circuit.Type: GrantFiled: April 30, 1998Date of Patent: April 25, 2000Assignee: Kabushiki Kaishi ToshibaInventors: Ken Takeuchi, Tomoharu Tanaka
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Patent number: 5969413Abstract: A semiconductor chip is supported on a tape carrier provided with lead wirings. The semiconductor chip is electrically connected to the lead wirings. The semiconductor chip of this quality is bonded in combination with the pe carrier to an aluminum nitride substrate. The lead wirings provided on the carrier combine the two functions as an internal lead and an external lead. The semiconductor package of such a structure as is described above allows multi-terminal connection by the narrowing of pitches between the leads and permits provision of a miniature package excelling in the heat-radiating property. Alternatively, the lead wirings supported on the tape carrier and electrically connected to the semiconductor chip are utilized as internal leads. For the external leads, such lead frames as are bonded to the aluminum nitride substrate are used. The lead frames are electrically connected to the internal leads provided in the tape carrier.Type: GrantFiled: May 14, 1997Date of Patent: October 19, 1999Assignee: Kabushiki Kaishi ToshibaInventors: Keiichi Yano, Kazuo Kimura, Hironori Asai, Jun Monma, Koji Yamakawa, Mitsuyoshi Endo, Hirohisa Osoguchi
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Patent number: 5905253Abstract: A memory card is to be inserted into an electronic device so as to add a memory function. The memory card comprises a parent card and a child card, the child card including a semiconductor memory element and a lead as an external terminal of the memory element. The parent card includes a child card receiving portion and a child card insert port for inserting the child card into the child card receiving portion through the child card insert port, and a contact to be contacted with the lead of the child card within the child card receiving portion. A contact opening/closing slide plate is provided for causing a contacting portion of the contact to be shifted to a position in which it can contact with the lead while moving in the child card insert direction pushed by the child card. The parent card also includes a connector element for contacting with the electronic device.Type: GrantFiled: September 21, 1995Date of Patent: May 18, 1999Assignees: Yamaichi Electronics Co., Ltd., Kabushiki Kaishi ToshibaInventors: Toshiyasu Ito, Hiroshi Iwasaki, Minoru Ohara
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Patent number: 5892213Abstract: A memory card is to be inserted into an electronic device so as to add a memory function. The memory card comprises a parent card and a child card, the child card including a semiconductor memory element and a lead as an external terminal of the memory element. The parent card includes a child card receiving portion and a child card insert port for inserting the child card into the child card receiving portion through the child card insert port, and a contact to be contacted with the lead of the child card within the child card receiving portion. A contact opening/closing slide is provided for causing a contacting portion of the contact to be shifted to a position in which it can contact with the lead while moving in the child card insert direction pushed by the child card. The parent card also includes a connector element for contacting with the electronic device.Type: GrantFiled: May 5, 1998Date of Patent: April 6, 1999Assignees: Yamaichi Electronics Co., Ltd., Kabushiki Kaishi ToshibaInventors: Toshiyasu Ito, Hiroshi Iwasaki, Minoru Ohara
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Patent number: 5875475Abstract: A continuous data server capable of reducing a cost for issuing control commands from a central control device to data memory control devices and communication control devices. The central control device issues a control command for each data memory control device and a control command for each communication control device collectively as a single control command set. Alternatively, the central control device issues control commands for the data memory control devices collectively as a single first control command set, and control commands for the communication control devices collectively as a single second control command set, through separately provided communication paths. When the continuous data are striped over data memory devices, the central control device can issue a common control command for all the data memory control devices.Type: GrantFiled: September 10, 1996Date of Patent: February 23, 1999Assignee: Kabushiki Kaishi ToshibaInventors: Toshiki Kizu, Tatsunori Kanai, Hiroshi Yao, Seiji Maeda