Patents Assigned to Kabushikia Kaisha Toshiba
  • Patent number: 7700381
    Abstract: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: April 20, 2010
    Assignee: Kabushikia Kaisha Toshiba
    Inventors: Tsunetoshi Arikado, Masao Iwase, Soichi Nadahara, Yuso Udo, Yukihiro Ushiku, Shinichi Nitta, Moriya Miyashita, Junji Sugamoto, Hiroaki Yamada, Hajime Nagano, Katsujiro Tanzawa, Hiroshi Matsushita, Norihiko Tsuchiya, Katsuya Okumura
  • Patent number: 6819596
    Abstract: In a method of testing a nonvolatile semiconductor memory integrated on a semiconductor chip comprising a memory cell array, a first register that stores an address of a defective region in the memory cell array, a plurality of internal voltage generator circuits, and a second register, the second register storing a trimming value for setting an internal voltage value generated by each of the internal voltage generator circuits, the testing method carries out resetting the address of the defective region stored in the first register and the trimming value stored in the second register, and setting the address of the defective region stored in the first register and the trimming value stored in the second register to a value according to a property of each of the semiconductor chips, wherein the testing is carried out without turning a power supply off after the power supply has been turned on.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: November 16, 2004
    Assignee: Kabushikia Kaisha Toshiba
    Inventors: Tamio Ikehashi, Ken Takeuchi, Toshihiko Himeno