Patents Assigned to Kabushiki Kaisha Toshiba
  • Patent number: 11984144
    Abstract: According to one embodiment, a disk device includes a magnetic head, a piezoelectric element and a flexure. The piezoelectric element includes two electrodes. The flexure includes a first part and a second part that swings. The first part has a first surface to which a first electrode is joined. The second part has a second surface to which the magnetic head is joined. The magnetic head has a third surface facing the first surface and the second surface. The first electrode is spaced apart from a second electrode in a first direction. The first surface and an end of the third surface face each other. The second surface and another end of the third surface face each other. A distance between the first surface and the one end of the third surface is longer than a distance between the second surface and the other end of the third surface.
    Type: Grant
    Filed: March 3, 2023
    Date of Patent: May 14, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Yusuke Nojima
  • Patent number: 11984143
    Abstract: According to one embodiment, among a plurality of magnetic heads, the larger the magnetic pole width of the magnetic pole of the magnetic head in the width direction of a recording track formed in a recording layer or the larger an area width of the magnetic head capable of reading the magnetic characteristics of an area of the recording layer on which magnetic recording has been carried out by means of the magnetic head, the farther is the magnetic head arranged outwardly from the vicinity of the center in the parallel arrangement direction of the magnetic disks.
    Type: Grant
    Filed: April 7, 2023
    Date of Patent: May 14, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Hiroshi Isokawa
  • Patent number: 11984588
    Abstract: According to one embodiment, there is provided an active material represented by a general formula Lix(NiaCobMncMd)1?s(Nb1?t?uTatM?u)sO2. Here, M is at least one selected from the group consisting of Li, Ca, Mg, Al, Ti, V, Cr, Zr, Mo, Hf, and W, M? is at least one selected from the group consisting of K, P, Fe, Si, Na, Cu and Zn, and 1.0?x?1.3, 0?a?0.9, 0?b?1.0, 0?c?0.8, 0?d?0.5, a+b+c+d=1, 0.005?s?0.3, 0.0005?t?0.1, and 0?u?0.3 are satisfied.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: May 14, 2024
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuya Sasakawa, Yasuhiro Harada, Norio Takami
  • Patent number: 11985897
    Abstract: A semiconductor device includes a semiconductor layer, a first electrode on a first surface of the semiconductor layer, a plurality of second electrodes on a second surface of the semiconductor layer, a control electrode between the first electrode and each of the plurality of second electrodes and electrically insulated from the semiconductor layer and each of the plurality of second electrodes, and a resin layer partially covering the second surface of the semiconductor layer and having a plurality of openings through which the respective second electrodes are at least partially exposed. Each of the plurality of openings has rounded corners. The device further includes a sensor element above the second surface of the semiconductor layer and covered by a first part of the resin layer surrounded by the openings.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: May 14, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Emiko Adachi, Yukie Nishikawa, Kotaro Zaima
  • Patent number: 11983465
    Abstract: An input assistance system includes a terminal device including a display screen, an acquisition unit, a recognition unit, an input item display unit, a recognition result display unit, and a reception unit. The acquisition unit acquires utterance voice data of a user. The recognition unit performs voice recognition of the utterance voice data to generate text data. The input item display unit displays a plurality of input items including the input item associated with the text data. The recognition result display unit displays the text data. The reception unit accepts an operation of selecting the input item associated with the text data displayed by the recognition result display unit from the plurality of input items displayed by the input item display unit. The reception unit accepts the operation of selecting the input item associated with the text data when the plurality of input items and the text data are displayed.
    Type: Grant
    Filed: February 3, 2023
    Date of Patent: May 14, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Digital Solutions Corporation
    Inventor: Ryouma Azami
  • Patent number: 11980975
    Abstract: According to one embodiment, a processing system includes a processing device. The processing device performs at least a first determination of determining whether or not a detector contacts a welding object. The detector includes a plurality of detection elements arranged in a first direction. The detector transmits an ultrasonic wave toward the welding object and detects a reflected wave. The first determination is based on a detection result when the reflected wave is detected by the detector.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: May 14, 2024
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masahiro Saito, Hiromasa Takahashi
  • Patent number: 11984142
    Abstract: According to one embodiment, a magnetic disk apparatus includes a magnetic disk, a magnetic head, and a controller. The magnetic disk is provided with a track including a plurality of first sectors. The controller accesses the magnetic disk by using the magnetic head. The plurality of first sectors includes a plurality of second sectors where data segments are written and a third sector where parity and first information indicating effectiveness or ineffectiveness of protection by the parity are written.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: May 14, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Kenji Ogawa
  • Patent number: 11984495
    Abstract: A semiconductor device of embodiments includes: a semiconductor layer having a first face and a second face opposite to the first face and including a first trench, a second trench, and a third trench provided on a first face side; a first gate electrode in the first trench; a second gate electrode in the second trench; a third gate electrode in the third trench; a fourth gate electrode and a fifth gate electrode provided on a second face side; a first electrode contacting the first face; a second electrode contacting the second face; a first electrode pad electrically connected to the first gate electrode; a second electrode pad electrically connected to the second gate electrode; a third electrode pad electrically connected to the third gate electrode; a fourth electrode pad electrically connected to the fourth gate electrode; and a fifth electrode pad electrically connected to the fifth gate electrode.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: May 14, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tomoko Matsudai, Yoko Iwakaji, Hiroko Itokazu
  • Patent number: 11983527
    Abstract: According to one embodiment, an electronic calculator includes a processor. The processor is configured to display a screen image on which a first area displaying a source code and a second area displaying a diagram representing at least a part of the source code are arranged and edit the diagram displayed in the second area.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: May 14, 2024
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hirotaka Toya, Mamoru Aoki, Hiroshi Fujimoto
  • Patent number: 11984473
    Abstract: A semiconductor device of embodiments includes: a transistor region including a semiconductor layer having a first face and a second face opposite to the first face, a first transistor having a first gate electrode provided on a first face side of the semiconductor layer, and a second transistor having a second gate electrode provided on a second face side of the semiconductor layer; and an adjacent region adjacent to the transistor region and including the semiconductor layer and a third transistor having a third gate electrode electrically connected to the second gate electrode and provided on the second face side of the semiconductor layer and the third transistor having an absolute value of a threshold voltage smaller than an absolute value of a threshold voltage of the second transistor.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: May 14, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tomoko Matsudai, Yoko Iwakaji
  • Patent number: 11984593
    Abstract: According to one embodiment, a secondary battery including a positive electrode, a negative electrode, an insulating layer, and a nonaqueous electrolyte is provided. The positive electrode includes a positive electrode active material-containing layer containing a lithium nickel cobalt manganese composite oxide. The negative electrode includes a negative electrode active material-containing layer having a first surface. The insulating layer includes a solid electrolyte layer having a second surface that is at least partly opposed to or partly in contact with the first surface and containing a Li ion conductive oxide. At least part of the second surface or the first and second surfaces includes a Mn-containing substance. An abundance ratio of Mn on the second surface is higher than that on the first surface.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: May 14, 2024
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keigo Hoshina, Yasunobu Yamashita, Shinsuke Matsuno
  • Patent number: 11981516
    Abstract: To solve the above problem, a control apparatus, a program, and a system that are capable of effectively providing picking information are provided. According to an embodiment, a control apparatus includes an image interface, a communication unit, and a processor. The image interface obtains an instruction image indicating information of articles to be picked. The communication unit transmits and receives data to and from a robot system that picks the articles. The processor generates picking information of the articles to be picked from the instruction image, and transmits the picking information to the robot system via the communication unit.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: May 14, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, Toshiba Infrastructure Systems & Solutions Corporation
    Inventor: Masaya Yaegashi
  • Patent number: 11983242
    Abstract: A learning data generation device includes an acquisition unit, an attention level derivation unit, and a selection unit. The acquisition unit acquires sequence data including a plurality of frames that include a target and are consecutive in a sequence. The attention level derivation unit derives an attention level that is feature data in a time axis direction of each of the plurality of frames included in the sequence data by using a trained model. The selection unit selects one or a plurality of frames included in the sequence data as a learning frame to be used for learning data based on the attention level.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: May 14, 2024
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroaki Tani
  • Patent number: 11983818
    Abstract: A measurement system includes a processor. Based on information measured by a camera that takes an image of a measurement target and an auxiliary object arranged on the measurement target, the processor acquires first point cloud data representing a three-dimensional geometry of the measurement target including the auxiliary object. Based on the first point cloud data and second point cloud data that is known and that represents a three-dimensional geometry of the measurement target, the processor eliminates point cloud data of the auxiliary object from the first point cloud data. The processor compares the first point cloud data, from which the point cloud data of the auxiliary object has been eliminated, with the second point cloud data. The processor displays information relating to a result of comparison on a display device.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: May 14, 2024
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yu Takeda, Hiroaki Nakamura
  • Patent number: 11983568
    Abstract: In a computing system in which resources are available for performance of computing tasks allocated to them, and tasks are requested by requesting computers, a scheduler is associated with each of the requesting computers, to enable that computer to obtain resource for performance of the tasks. Each scheduler obtains resources, in accordance with a locally formulated preference list of resources, on the basis of scheduling tokens issued by resources indicative of reciprocal prioritisation of tasks by resources.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: May 14, 2024
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ziming Zhu
  • Patent number: 11984387
    Abstract: A first chip includes a first surface, a second surface, a first semiconductor layer including a nitride semiconductor layer, a first electrode pad located at the first surface, a second electrode pad located at the first surface, a first gate pad located at the first surface, and a third electrode pad located at the first surface. A second chip is located on the first surface of the first chip. The second chip includes a third surface facing the first surface of the first chip, a fourth surface, a second semiconductor layer including a channel of a second conductivity type, a fourth electrode pad located at the fourth surface, a fifth electrode pad located at the third surface and bonded to the second electrode pad of the first chip, and a second gate pad located at the third surface and bonded to the third electrode pad of the first chip.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: May 14, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Toru Sugiyama, Akira Yoshioka, Yasuhiro Isobe
  • Publication number: 20240149546
    Abstract: A rubber mold according to an embodiment is for CIP processing of a green compact with a plate shape. The rubber mold includes one or more approximately columnar hole sections are provided on at least one or more bottom surfaces. Further, when a diameter of an opening of the hole section is denoted by a and a maximum depth of the hole section is denoted by b, a/b<2.0 is satisfied.
    Type: Application
    Filed: January 19, 2024
    Publication date: May 9, 2024
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Kai FUNAKI, Yoshiyuki FUKUDA, Koji HASEGAWA
  • Publication number: 20240154004
    Abstract: According to one embodiment, a nitride semiconductor includes a nitride member. The nitride member include a first nitride region, a second nitride region, and intermediate region. The first nitride region includes Alx1Ga1?x1N (0?x1<1). The Alx1Ga1?x1N includes a first element including at least one selected from the group consisting of Fe and Mn. The second nitride region includes Alx2Ga1?x2N (0?x2?1). A direction from the first nitride region to the second nitride region is along a first direction. The intermediate region is provided between the first nitride region and the second nitride region. The intermediate region includes Alz1Ga1?z1N (0?z1?1, x1<z1, x2<z1). The Alz1Ga1?z1N includes oxygen. A concentration of oxygen in the nitride member becomes maximum in the intermediate region.
    Type: Application
    Filed: July 28, 2023
    Publication date: May 9, 2024
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION
    Inventor: Toshiki HIKOSAKA
  • Publication number: 20240152132
    Abstract: An information processing apparatus comprising processing circuitry, the processing circuitry constructs a prediction model for predicting time-series data related to a state of a device/equipment, calculates a prediction error that is a difference between a predicted value of the time-series data predicted by the prediction model and an actual value of the time-series data, divides the prediction error into a plurality of first sections in a time axis direction, calculates a state change amount of the actual value based on the prediction error divided into the plurality of first sections; and constructs a state determination model for determining the state of the device/equipment based on the state change amount.
    Type: Application
    Filed: September 13, 2023
    Publication date: May 9, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Topon PAUL, Reddy VIDHISHA, Ayyagari Sai Prem KUMAR, Kaneharu NISHINO
  • Publication number: 20240152533
    Abstract: According to one embodiment, an information processing method includes, based on a metamodel which is located in a first layer and in which a composition relationship and a reference relationship among plural types of information models located in a second layer are defined, creating a guide tree indicating a relationship between the information models. A data item (property) of data related to devices is defined in the information model. The guide tree indicates that an upper-layer first information model in which a relationship is indicated in the guide tree is able to use a data item defined in a lower-layer second information model.
    Type: Application
    Filed: September 12, 2023
    Publication date: May 9, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Lan YAMASHITA, Mikito IWAMASA, Koji FUJIWARA