Patents Assigned to KAISHA TOSHIBA
  • Patent number: 11097316
    Abstract: According to one embodiment, a sorting system has a delivery processing apparatus, a video coding terminal, and a recognition support apparatus. The recognition support apparatus has an information management portion, a correct solution derivation portion, and a machine learning portion. The information management portion acquires an image obtained by imaging a delivery object and keying information. The correct solution derivation portion derives respective correct solutions for a plurality of processings for the image obtained by imaging the delivery object, based on the keying information acquired by the information management portion. The machine learning portion performs machine learning using the respective correct solutions for the plurality of processings derived by the correct solution derivation portion, to adjust the plurality of processings.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: August 24, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Infrastructure Systems & Solutions Corporation
    Inventors: Yasuhiro Ohkawa, Tomoyuki Hamamura, Takuma Akagi
  • Patent number: 11098409
    Abstract: An electrolytic cell for carbon dioxide of an embodiment includes: an anode part including an anode to oxidize water or a hydroxide ion and thus produce oxygen and an anode solution flow path to supply an anode solution to the anode; a cathode part including a cathode to reduce carbon dioxide and thus produce a carbon compound, a cathode solution flow path to supply a cathode solution to the cathode, and a liquid passing member disposed between the cathode and the cathode solution flow path and having a pore allowing the cathode solution to pass through while holding the cathode solution; and a separator to separate the anode part and the cathode part from each other.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: August 24, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuki Kudo, Akihiko Ono, Masakazu Yamagiwa, Ryota Kitagawa, Jun Tamura, Yoshitsune Sugano, Asahi Motoshige, Satoshi Mikoshiba
  • Patent number: 11101388
    Abstract: A semiconductor device of an embodiment includes a semiconductor layer having a first plane, a second plane, and a through hole penetrating from the first plane to the second plane; an insulating layer on a side of the second plane of the semiconductor layer; a first conductive layer in the insulating layer; a silicon oxide layer on a side of the first plane and in the through hole; a silicon nitride layer provided on the side of the first plane and in the through hole, the silicon oxide layer being interposed between the silicon nitride layer and the semiconductor layer; and a second conductive layer on the side of the first plane and in the through hole, the silicon oxide layer and the silicon nitride layer being interposed between the second conductive layer and the semiconductor layer, and the second conductive layer electrically connected to the first conductive layer.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: August 24, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hirofumi Baba
  • Patent number: 11102367
    Abstract: According to one embodiment, an information processing method includes instructing a multifunction peripheral performing scanning and printing to perform setting regarding scanning, transmitting a scan signal for performing scanning to the multifunction peripheral, instructing the multifunction peripheral to perform setting regarding printing, and transmitting a print signal for printing a scan image obtained through scanning to the multifunction peripheral.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: August 24, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA TEC KABUSHIKI KAISHA
    Inventor: Daiki Sakamoto
  • Patent number: 11101383
    Abstract: A semiconductor device of an embodiment includes: a first semiconductor layer of a first conductive type; a second semiconductor layer of the first conductive type, being provided on the first semiconductor layer and including a first trench, a plurality of holes, a plurality of second trenches, and a plurality of third trenches; a first semiconductor region of a second conductive type, being provided on the second semiconductor layer; a second semiconductor region of the first conductive type, being provided on the first semiconductor region; a first electrode electrically connected to the second semiconductor region; a second electrode disposed in the first trench via a first insulation film; a plurality of first field plate electrodes having a column shape, being electrically connected to the first electrode, interposing the second electrode, and being disposed in the holes via a second insulation film; a plurality of third electrodes extending from ends of the first insulation films in a first direction t
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: August 24, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Tatsuya Nishiwaki
  • Patent number: 11101780
    Abstract: According to an embodiment, a comparator circuit includes first and second PMOS transistors that compose a differential pair, a first switching transistor with a main current path that is connected between an input terminal and a gate of the first PMOS transistor, a voltage source that applies a reference voltage to a gate of the second PMOS transistor, and a first bias circuit that applies a first bias voltage to a control electrode of the first switching transistor.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: August 24, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Masaaki Morikawa
  • Patent number: 11101355
    Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer, an insulating layer provided on the nitride semiconductor layer, a first region provided in the nitride semiconductor layer, and a second region which is provided between the first region in the nitride semiconductor layer and the insulating layer, has a higher electric resistivity than the first region, and includes carbon (C).
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: August 24, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuo Shimizu
  • Patent number: 11100662
    Abstract: According to one embodiment, an image processing apparatus includes a memory and one or more hardware processors electrically coupled to the memory. The one or more hardware processors acquire a first image of an object including a first shaped blur and a second image of the object including a second shaped blur. The first image and the second image are acquired by capturing at a time through a single image-forming optical system. The one or more hardware processors acquire distance information to the object based on the first image and the second image, with a statistical model that has learnt previously.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: August 24, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nao Mishima, Takayuki Sasaki
  • Patent number: 11097756
    Abstract: According to one embodiment, a moving block signaling headway calculation system recursively executes a process until an interval reaches a limit value. The process includes calculating headway values for a plurality of points on the running section for each interval, extracting a section between adjacent two points, in which an amount of variation in the headway values between the adjacent two points exceeds a threshold value, a section between two points before and after a front point and an end point of a point or a section where a headway value changes from rise to fall, or a section between two points before and after a front point and an end point of a point or a section where a headway value changes from fall to rise, and subdividing the interval in the extracted sections.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: August 24, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA DIGITAL SOLUTIONS CORPORATION
    Inventor: Hideki Kubo
  • Patent number: 11100947
    Abstract: According to one embodiment, a magnetic disk device includes a disk including a servo sector including burst data, a head including a write head which writes data to the disk, and a read head which reads data from the disk, and a controller which generates a first normal servo gate for applying servo read to the servo sector, wherein when a short servo gate for at least applying servo read to the burst data is generated, the controller generates the short servo gate and the first normal servo gate, and when the short servo gate is not generated, the controller generates the first normal servo gate and a second normal servo gate different from the first normal servo gate.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: August 24, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Naoki Tagami
  • Patent number: 11102148
    Abstract: A device for computing a routing path from a source node to a destination node across a 6TISCH mesh network comprising a plurality of nodes, the device comprising: an interface for communicating with one or more nodes in the network; a memory configured to store data regarding the stability and availability of individual nodes in said network to receive packet data; a controller configured to: employ said data regarding the stability and availability of individual nodes in said network to receive packet data to calculate a path stability metric for each of a plurality of potential routing paths between said source node and said destination node, employ said path stability metric to select one of said plurality of potential routing paths for data transmission between said source node and said destination node, and cause said interface to transmit a signal configured to cause said plurality of nodes to transmit data from said source node to said destination node via said selected route.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: August 24, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yichao Jin
  • Patent number: 11097620
    Abstract: A circuit system for a railroad vehicle according to an embodiment includes a power conversion unit, a first converter, a second converter, a power storage unit, and a control unit. The power conversion unit converts power supplied from an overhead wire into power for driving a motor for running mounted on a railroad vehicle. The first converter converts power supplied from the overhead wire into DC power. The second converter converts power output from the first converter into power for driving a load mounted on the railroad vehicle. The power storage unit is electrically connected to an input side of the second converter. The control unit inputs regenerative power output from the power conversion unit to the first converter and inputs power output from the first converter to the power storage unit in a case where it is determined that the railroad vehicle is being regenerated.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: August 24, 2021
    Assignees: Kabushiki Kaisha Toshiba, TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION
    Inventors: Kohei Yamamoto, Sakio Nishimiya, Sonoko Miyajiri, Sho Sato, Hideyuki Shimizu, Kazuaki Yuuki, Tomoyuki Makino
  • Publication number: 20210256325
    Abstract: An image processing apparatus according to an embodiment includes a processor. The processor acquires a classification result of classifying each of a plurality of regions set in a processing target image into one of a plurality of predetermined classes. The processor converts multidimensional data corresponding to each of the plurality of regions set in the image into low-dimensional data. The processor causes a display image including one or more regions to be displayed together with a plotted diagram including a plurality of plot points having different colors or patterns applied according to the classification result to the low-dimensional data in each of the plurality of regions, and in a case where an instruction for selecting a selected point from among the plot points is issued, the processor performs a discriminative display causing the selected point and a region corresponding to the selected point in the display image to be visually identifiable.
    Type: Application
    Filed: May 3, 2021
    Publication date: August 19, 2021
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Digital Solutions Corporation
    Inventors: Yeonsoo YANG, Tamotsu SATO, Hiroyuki MIZUTANI
  • Publication number: 20210256676
    Abstract: An inspection apparatus including an image generation device which generates a second image corresponding to a first image, and a defect detection device which detects a defect in the second image. Each of the first and second image includes partial regions each including pixels. The defect detection device is configured to estimate a first value indicating a position difference between the first and second image for each of the partial regions, based on a luminance difference between the first and second image, estimate a second value indicating a reliability of the first value for each of the partial regions, and estimate a position difference between the first and second image for each of the pixels, based on the first and second value estimated for each of the partial regions.
    Type: Application
    Filed: August 31, 2020
    Publication date: August 19, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideaki OKANO, Takeshi MORINO, Yoshinori HONGUH
  • Publication number: 20210256109
    Abstract: An information processing device includes a first communication unit, a second communication unit, an information processing unit, and a switching unit. The first communication unit is configured to communicate with a terminal device. The second communication unit is configured to communicate with a device connected to a network. The information processing unit is configured to encrypt information which is received from the terminal device by the first communication unit and to transmit the encrypted information to the network via the second communication unit, and is configured to decrypt information which is received from the network by the second communication unit and to transmit the decrypted information to the terminal device via the first communication unit.
    Type: Application
    Filed: April 9, 2021
    Publication date: August 19, 2021
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Infrastructure Systems & Solutions Corporation
    Inventor: Yusuke YAGI
  • Publication number: 20210256972
    Abstract: According to one embodiment, the interface-providing apparatus comprises an identifying unit and a generating unit. The identifying unit identifies a keyword from dialogue data including a question text to request information, and a response text in reply thereto. The generating unit generates display information to display a user interface for receiving feedback input relating to a degree of usefulness of a keyword when searching for the requested information.
    Type: Application
    Filed: August 31, 2020
    Publication date: August 19, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenji IWATA, Hiroshi FUJIMURA, Takami YOSHIDA
  • Publication number: 20210253368
    Abstract: A holding device includes a supporter, a gripper, and a first driver. The supporter supports a weight of a workpiece in a first direction. The gripper includes a gripping surface that grips the workpiece in a second direction crossing the first direction. The first driver moves the supporter with respect to the gripper in the second direction. A tilt of the supporter is changeable with respect to the gripping surface along a plane including the first and second directions.
    Type: Application
    Filed: February 16, 2021
    Publication date: August 19, 2021
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION
    Inventors: Yukihiro IKEYA, Takeshi TOYOSHIMA, Taketo SHIBA
  • Publication number: 20210257469
    Abstract: According to one embodiment, a semiconductor device includes first, second and third conductive parts, a first semiconductor region, and a first insulating part. A direction from the first conductive part toward the second conductive part is along a first direction. The first semiconductor region includes first, second, and third partial regions. A second direction from the first partial region toward the second partial region crosses the first direction. The third partial region is between the first partial region and the second conductive part in the first direction. The third partial region includes an opposing surface facing the second conductive part. A direction from the opposing surface toward the third conductive part is along the second direction. The first insulating part includes a first insulating region. At least a portion of the first insulating region is between the opposing surface and the third conductive part.
    Type: Application
    Filed: September 9, 2020
    Publication date: August 19, 2021
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tomoaki INOKUCHI, Hiro GANGI, Yusuke KOBAYASHI, Masahiko KURAGUCHI, Kazuto TAKAO, Ryosuke IIJIMA, Tatsuo SHIMIZU, Tatsuya NISHIWAKI
  • Publication number: 20210257919
    Abstract: A power conversion device includes a first switching element and a first inductor connected in series between a first terminal and a second terminal, the first inductor and a second switching element being connected in series between the second and third terminals, a switching controller that alternately turns on and off the first and second switching elements, a first capacitor connected between the first and second terminals, and a second capacitor connected between the second and third terminals. When a first full-wave rectified voltage is input, switching frequencies of the first switching element and the second switching element, an inductance of the first inductor, a capacitance of the first capacitor, and a capacitance of the second capacitor are set so that a second full-wave rectified voltage having a voltage amplitude and a phase same as the voltage amplitude and the phase of the first full-wave rectified voltage is output.
    Type: Application
    Filed: September 8, 2020
    Publication date: August 19, 2021
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yusuke HAYASHI, Kazuto TAKAO
  • Patent number: 11095256
    Abstract: A semiconductor device includes three transistors, five switches, two inductors, and a capacitor. A first transistor has a gate. The switches have one terminal connected in series with a drain of the first transistor in parallel. A second transistor has a source connected to the first switch and a grounded gate. A third transistor having a source connected to the second switch and a grounded gate. A first inductor and a second inductor each has one terminal connected in series with the third switch in parallel. A fourth switch has one terminal connected to the first inductor and another terminal connected to the source of the second transistor. A fifth switch has one terminal connected to the second inductor and another terminal connected to the source of the third transistor. A capacitor connected between the one terminal of the fourth switch and the one terminal of the fifth switch.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: August 17, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Toshiki Seshita, Yasuhiko Kuriyama