Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.
Type:
Grant
Filed:
March 1, 2012
Date of Patent:
February 18, 2014
Assignee:
Kamet Electronics Corporation
Inventors:
John D. Prymak, Chris Stolarski, Alethla Melody, Antony P. Chacko, Gregory J. Dunn