Abstract: Methods and systems are described for obtaining a set of carrier-modulated symbols of a carrier-modulated codeword, each carrier-modulated symbol received via a respective wire of a plurality of wires of a multi-wire bus, applying each carrier-modulated symbol of the set of carrier-modulated symbols to a corresponding transistor of a set of transistors, the set of transistors further connected to a pair of output nodes according to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors, recovering a demodulation signal from the carrier-modulated symbols, and generating a demodulated sub-channel data output as a differential voltage on the pair of output nodes based on a linear combination of the set of carrier-modulated symbols by controlling conductivity of the set of transistors according to the demodulation signal.

Abstract: Interleaved Forward Error Correction (FEC) encoded data from multiple FEC encoders for transport over a multi-channel physical transport medium, with cyclical rotation of the FEC encoded data bytes across transport channels in a given transmission interval as well as across time within each transport channel. A plurality of parallel FEC encoders are used to generate respective parallel FEC-encoded data streams, the outputs of which are then interleaved across a plurality of transport channels in a given transmission time interval, and, within each transport channel, the interleaved order varies over the time intervals.

Abstract: Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.

Abstract: Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.

Abstract: Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal from a plurality of data-driven phase-error signals generated using phase detectors in a plurality of receivers configured as ODVS sub-channel MICs generating orthogonal sub-channel outputs in a first mode and a separate first and second data driven phase-error signal from two receivers of a plurality of receivers configured as NRZ receivers in a second mode.

Abstract: Obtaining a periodic test signal, sampling the periodic test signal using a sampling element according to a sampling clock to generate a sampled periodic output, the sampling element operating according to a supply voltage provided by a voltage regulator, the voltage regulator providing the supply voltage according to a supply voltage control signal, comparing the sampled periodic output to the sampling clock to generate a clock-to-Q measurement indicative of a delay value associated with the generation of the sampled periodic output in response to the sampling clock, generating the supply voltage control signal based at least in part on an average of the clock-to-Q measurement, and providing the supply voltage to a data sampling element connected to the voltage regulator, the data sampling element being a replica of the sampling element, the data sampling element sampling a stream of input data according to the sampling clock.

Abstract: Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

Abstract: Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.

Abstract: Methods are described allowing a vector signaling code to encode multi-level data without the significant alphabet size increase known to cause symbol dynamic range compression and thus increased noise susceptibility. By intentionally restricting the number of codewords used, good pin efficiency may be maintained along with improved system signal-to-noise ratio.

Abstract: A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.

Abstract: Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.

Abstract: An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herein called the “ISI Ratio” are described which permit higher communications speed, lower system power consumption, and reduced implementation complexity.

Abstract: Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.

Abstract: Methods and systems are described for receiving an input data voltage signal at a first data decision circuit of set of pipelined data decision circuits, receiving an aggregate decision feedback equalization (DFE) correction current signal from a first analog current summation bus, the aggregate DFE correction current signal comprising a plurality of DFE tap-weighted currents from respective other data decision circuits of the set of pipelined data decision circuits, determining a data output decision value based on the received input data voltage signal and the received aggregate DFE correction current signal, and generating at least one outbound DFE tap-weighted current on at least one other analog current summation bus connected to at least one other data decision circuit of the set of pipelined data decision circuits.

Abstract: Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error decision, the phase error decision selected in response to identification of a predetermined data decision pattern.

Abstract: Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

Abstract: Methods and systems are described for generating a time-varying information signal at an output of a variable gain amplifier (VGA), sampling, using a sampler having a vertical decision threshold associated with a target signal amplitude, the time-varying information signal asynchronously to generate a sequence of decisions from varying sampling instants in sequential signaling intervals, the sequence of decisions comprising (i) positive decisions indicating the time-varying information signal is above the target signal amplitude and (ii) negative decisions indicating the time-varying information signal is below the target signal amplitude, accumulating a ratio of positive decisions to negative decisions, and generating a gain feedback control signal to adjust a gain setting of the VGA responsive to a mismatch of the accumulated ratio with respect to a target ratio.

Abstract: Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

Abstract: Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

Abstract: Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.