Abstract: Methods and systems are described for receiving signal elements corresponding to a first group of symbols of a vector signaling codeword over a first densely-routed wire group of a multi-wire bus at a first set of multi-input comparators (MICs), receiving signal elements corresponding to a second group of symbols of the vector signaling codeword over a second densely-routed wire group of the multi-wire bus at a second set of MICs, and receiving signal elements corresponding to the first and the second groups of symbols of the vector signaling codeword at a global MIC.

Abstract: Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct data and clocking signals over the same transport medium. Embodiments are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.

Abstract: Methods and systems are described for receiving a plurality of signals in a signaling interval at a multi-input comparator (MIC), and responsively generating an analog linear combination of the received signals, amplifying the analog linear combination of the received signals using an integration stage, receiving the amplified differential voltage at two multi-phase receivers, each multi-phase receiver comprising one or more processing slices, each multi-phase receiver operating in a multi-phase processing path for processing the amplified differential voltage, wherein processing the amplified differential voltage includes generating output data decisions and phase-error information using a first multi-phase receiver of the two multi-phase receivers and selectively adjusting local speculative decision feedback equalization (DFE) slicing offsets of a second multi-phase receiver of the two multi-phase receivers according to the output data decisions generated by the first multi-phase receiver.

Abstract: Pre-charging two or more sets of nodes to set a differential output of a multi-input summation latch connected to the two or more sets of nodes in a pre-charged state, the two or more sets of nodes comprising a set of data signal nodes and a set of DFE correction nodes, in response to a sampling clock, generating a differential data voltage and an aggregate differential DFE correction signal, and generating a data decision by driving the differential output of the multi-input summation latch into one of two possible output states according to a summation of the differential data voltage signal and the aggregate differential DFE correction signal and subsequently holding the data decision by holding the differential output of the multi-input summation latch in a latched state for a duration determined by the sampling clock.

Abstract: Vector signaling codes are synergistically combined with multi-level signaling, the increased alphabet size provided by the multi-level signaling enabling a larger codeword space for a given number of symbols, at the cost of reduced receiver detection margin for each of the multiple signal levels. Vector signaling code construction methods are disclosed in which code construction and selection of multi-level signal levels are coordinated with the design of an associated receive comparator network, wherein modified signal levels encoded and emitted by the transmitter result in increased detection margin at the receive comparators.

Abstract: Advanced detectors for vector signaling codes are disclosed which utilize multi-input comparators, generalized on-level slicing, reference generation based on maximum swing, and reference generation based on recent values. Vector signaling codes communicate information as groups of symbols which, when transmitted over multiple communications channels, may be received as mixed sets of symbols from different transmission groups due to propagation time variations between channels. Systems and methods are disclosed which compensate receivers and transmitters for these effects and/or utilize codes having increased immunity to such variations, and circuits are described that efficiently implement their component functions.

Abstract: Methods and systems are described for receiving a signal to be sampled and responsively generating, at a pair of common nodes, a differential current representative of the received signal, receiving a plurality of sampling interval signals, each sampling interval signal received at a corresponding sampling phase of a plurality of sampling phases, for each sampling phase, pre-charging a corresponding pair of output nodes using a pre-charging FET pair receiving the sampling interval signal, forming a differential output voltage by discharging the corresponding pair of output nodes via a discharging FET pair connected to the pair of common nodes, the FET pair receiving the sampling interval signal and selectively enabling the differential current to discharge the corresponding pair of output nodes, and latching the differential output voltage.

Abstract: Methods and systems are described for generating, with a local oscillator and an adjustable phase interpolator, a data-sampling clock and a variable-phase-offset eye-measurement clock, forming a received data signal using a multi-input comparator, generating, using a data slicer and the data sampling clock, a receive sample of the received data signal, and generating, using at least one eye slicer and the variable-phase-offset eye-measurement clock, a plurality of eye characteristic measurements by adjusting a sampling threshold of the at least one eye slicer and a phase offset of the variable-phase-offset eye-measurement clock.

Abstract: Described herein are systems and methods of receiving first and second input signals at a first two-input comparator, responsively generating a first subchannel output, receiving third and fourth input signals at a second two-input comparator, responsively generating a second subchannel output, receiving the first, second, third, and fourth input signals at a third multi-input comparator, responsively generating a third subchannel output representing a comparison of an average of the first and second input signals to an average of the third and fourth input signals, configuring a first data detector connected to the second subchannel output and a second data detector connected to the third subchannel output according to a legacy mode of operation and a P4 mode of operation.

Abstract: Methods and systems are described for receiving, over a plurality of consecutive signaling intervals, a plurality of codewords, each codeword received as a plurality of symbols via wires of a multi-wire bus, the plurality of symbols received at a plurality of multi-input comparators (MICs), wherein each symbol is received by at least two MICs, generating, for each codeword, a corresponding linear combination of the received symbols, generating a plurality of composite skew measurement signals over the plurality of consecutive signaling intervals, each composite skew measurement signal based on samples of one or more linear combinations, and updating wire-specific skew values of the wires of the multi-wire bus, wherein one or more wire-specific skew values are updated according to composite skew measurement signals associated with linear combinations formed by at least two different MICs.

Abstract: Methods and systems are described for receiving a sampling signal, pre-charging a pair of output nodes prior to a sampling interval, initiating the sampling interval by enabling a current source according to a first transition of the received sampling signal, generating a differential output voltage at the pair of output nodes by discharging the pair of output nodes according to a differential input signal, the pair of output nodes discharged according to current drawn by the current source during the sampling interval, terminating the sampling interval by disabling the current source in response to a second transition of the received sampling signal, and inhibiting a recharge of the pair of output nodes for a hold time after termination of the sampling interval and prior to initiation of a subsequent sampling interval.

Abstract: Multi-drop communications channels can have significantly deep notches in their frequency response causing a corresponding limitation of the effective data transmission rate. A special time-ordered coding method is described which results in the emitted spectrum of the data stream transmitted into the channel having a notch at the same frequency as the notch in the channel frequency response, permitting channel receivers to successfully decode the transmitted data stream. The described coding method may be applied at various multiples of the channel notch frequency to support different throughput rates, and may be combined with other coding techniques such as group or vector signaling codes.

Abstract: Methods and systems are described for receiving a control step input at a binary-to-thermometer decoder and responsively generating bits of a thermometer codeword representative of the control step input, providing the bits of the thermometer codeword to a plurality of differential pairs comprising a first transistor and a second transistor, each differential pair configurable for one of directing current to an in-phase (I) common node or directing current to a quadrature phase (Q) common node and switching between directing current to the I common node and the Q common node, and forming an output signal based on current drawn through the I and Q common nodes, the output signal having an intermediate phase with respect to a first and a second reference signal.

Abstract: Generating first and second discharge control signals in response to a clock signal and an input voltage signal, the first and second discharge control signals decreasing at different rates to a threshold level during a first time period, wherein a difference in rates is determined by the input voltage signal, generating a differential voltage on a pair of nodes during the first time period by selectively controlling a respective amount of discharge of an initial charge on each node of the pair of nodes by applying the first and second discharge control signals to respective transistors in a differential transistor pair connected to the pair of nodes, and maintaining the differential voltage on the pair of nodes during a subsequent time period, and generating an amplified differential voltage during at least a portion of the subsequent time period by amplifying the differential voltage.

Abstract: Generating, at a plurality of delay stages of a local oscillator, a plurality of phases of a local oscillator signal, generating a loop error signal based on a comparison of one or more phases of the local oscillator signal to one or more phases of a received reference clock, generating a plurality of phase-specific quadrature error signals, each phase-specific quadrature error signal associated with a respective phase of the plurality of phases of the local oscillator signal, each phase-specific quadrature error signal based on a comparison of the respective phase to two or more other phases of the local oscillator signal, and adjusting each delay stage according to a corresponding phase-specific quadrature error signal of the plurality of phase-specific quadrature error signals and the loop error signal.

Abstract: Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error indication, the phase error indication selected in response to identification of a predetermined data decision pattern.

Abstract: Methods and systems are described for reduction of crosstalk in multi-wire communications systems using ensemble codes. Constraints applied to code construction and/or permissible encoding sequences eliminate transmit patterns shown to generate capacitively coupled and/or inductively coupled crosstalk.

Abstract: In a detection circuit, inputs correspond to received indications of vector signaling code words received by a first integrated circuit from a second integrated circuit. With four inputs, the circuit compares a first pair to obtain a first difference result and compares a second pair, disjoint from the first pair, to obtain a second difference result. The first and second difference results are then summed to form an output function. A system might use a plurality of such detection circuits to arrive at an input word. The circuit can include amplification, equalization, and input selection with efficient code word detection. The vector signaling code can be a Hadamard matrix code encoding for three input bits. The circuit might also have frequency-dependent gain, a selection function that directs one of the summation function result or the first difference result to the output function, variable gain, and/or a slicer.

Abstract: Methods and systems described include a first dielectric material having a plurality of embedded conductors of a multi-wire channel, the plurality of embedded conductors comprising at least a first, second and third conductor, wherein a first distance between the first and second conductors is less than a second distance between the first and third conductors, wherein the first dielectric material has a first dielectric constant ?1 and a second dielectric material embedded in the first dielectric material, the second dielectric material embedded in between the first and third conductors, the second dielectric material having a second dielectric constant ?2, wherein ?2>?1.

Abstract: Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.