Patents Assigned to Kanto Sanyo Semiconductor Co., Ltd.
  • Publication number: 20080093708
    Abstract: A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate bonded to a supporting body through an insulation film and a resin is increased to prevent cracks in the supporting body and separation of the semiconductor substrate from the supporting body. A slit is formed along a dicing line after forming the window, the slit is covered with a protection film and then the semiconductor substrate is diced into individual semiconductor dice. Thus, separation on a cut surface or at an edge of the semiconductor dice, which otherwise would be caused by contact of the blade in the dicing can be prevented.
    Type: Application
    Filed: December 13, 2007
    Publication date: April 24, 2008
    Applicants: SANYO Electric Co., Ltd., Kanto SANYO Semiconductor Co., Ltd.
    Inventors: Takashi Noma, Katsuhiko Kitagawa, Hisao Otsuka, Akira Suzuki, Yoshinori Seki, Yukihiro Takao, Keiichi Yamaguchi, Motoaki Wakui, Masanori Iida
  • Publication number: 20080073763
    Abstract: An object of the present invention is to improve heat dissipation of a semiconductor device, thereby preventing a semiconductor device from being destroyed by heat generation. To this end, provided is a semiconductor device including a lead frame, a semiconductor chip, and an island to which the semiconductor chip is fixed. In the semiconductor device, a recessed portion is formed in a center portion of the island, while the semiconductor chip is fixed to a peripheral portion of the island. According to this configuration, the recessed portion of the island is exposed to the outside of the package of the semiconductor device, or is located near the surface of the package. Accordingly, the recessed portion of the island absorbs heat generated from the semiconductor chip, and then dissipates the heat to the outside. As a result, the semiconductor device is prevented from being destroyed by the heat generation.
    Type: Application
    Filed: September 25, 2007
    Publication date: March 27, 2008
    Applicants: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd., Kanto SANYO Semiconductors Co., Ltd.
    Inventor: Wasarin Jungsuwadee
  • Patent number: 7339273
    Abstract: The invention is directed to a semiconductor device having a penetrating electrode and a manufacturing method thereof in which reliability and a yield of the semiconductor device are enhanced. A semiconductor substrate is etched to form a via hole from a back surface of the semiconductor substrate to a pad electrode. This etching is performed under an etching condition such that an opening diameter of the via hole at its bottom is larger than a width of the pad electrode. Next, a second insulation film is formed on the back surface of the semiconductor substrate including in the via hole 16, exposing the pad electrode at the bottom of the via hole. Next, a penetrating electrode and a wiring layer are formed, being electrically connected with the pad electrode exposed at the bottom of the via hole 16. Furthermore, a protection layer and a conductive terminal are formed. Finally, the semiconductor substrate is cut and separated in semiconductor dies by dicing.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: March 4, 2008
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Kojiro Kameyama, Akira Suzuki, Mitsuo Umemoto
  • Patent number: 7332803
    Abstract: A circuit device is provided comprising leads and electrical circuitry. The circuit device has a first semiconductor element, a second semiconductor element, first leads electrically connected to the first semiconductor element or the second semiconductor element via fine metal wires and having an end thereof extending outwardly, second leads electrically connected via metal wires to both the first semiconductor element and the second semiconductor element to thus electrically connect the first and second semiconductor elements.
    Type: Grant
    Filed: July 26, 2004
    Date of Patent: February 19, 2008
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Makoto Tsubonoya, Katsuhiko Shibusawa, Takashi Kitazawa
  • Patent number: 7317199
    Abstract: To provide a circuit device suitable for incorporating a semiconductor element emitting or receiving short-wavelength light. The circuit device includes a casing, a semiconductor element, and a cover portion. The casing has an opening on the top face thereof. The semiconductor element is incorporated in the casing and emits or receives light. The cover portion is made of a material transparent to the light and covers the opening. In the periphery of the opening, a concave portion is provided, and a portion of the cover portion with a certain thickness on the bottom side is accommodated in the concave portion. Since the portion of the cover portion with the certain thickness on the bottom side is accommodated in the concave portion provided in the upper portion of the casing, the position of the cover portion is accurately fixed. Accordingly, it is possible to obtain accurate relative positions of the semiconductor element accommodated within the casing and the cover portion.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: January 8, 2008
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductor Co., Ltd.
    Inventor: Hiroshi Inoguchi
  • Patent number: 7312107
    Abstract: A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate bonded to a supporting body through an insulation film and a resin is increased to prevent cracks in the supporting body and separation of the semiconductor substrate from the supporting body. A slit is formed along a dicing line after forming the window, the slit is covered with a protection film and then the semiconductor substrate is diced into individual semiconductor dice. Thus, separation on a cut surface or at an edge of the semiconductor dice, which otherwise would be caused by contact of the blade in the dicing can be prevented.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: December 25, 2007
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Takashi Noma, Katsuhiko Kitagawa, Hisao Otsuka, Akira Suzuki, Yoshinori Seki, Yukihiro Takao, Keiichi Yamaguchi, Motoaki Wakui, Masanori Iida
  • Patent number: 7307288
    Abstract: A semiconductor device capable of incorporating an element configured to accept and emit light having a short wavelength and a manufacturing method thereof are provided. A semiconductor element is housed in an enclosure which includes a bottom portion and side portions and having an aperture on an upper part thereof. Leads are buried in the bottom portion, and an end of each of the leads is arranged so as to approach the semiconductor element. The semiconductor element is connected to the leads by use of metal wires. The aperture of the enclosure is covered with a lid made of a transparent material for transmitting light accepted or emitted by the semiconductor element.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: December 11, 2007
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventor: Hiroshi Inoguchi
  • Patent number: 7301228
    Abstract: The present invention provides a low-profile and light-weight semiconductor device having improved product reliability and higher frequency performance. A multi-layer interconnect line structure is disposed just under circuit devices 410a and 410b. An Interlayer insulating film 405 that composes a part of the multi-layer interconnect line structure is formed of a material having a relative dielectric constant within a range from 1.0 to 3.7, and a dielectric loss tangent within a range from 0.0001 to 0.02.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: November 27, 2007
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Noriaki Kojima, Noriaki Sakamoto
  • Patent number: 7264997
    Abstract: A semiconductor device comprises a semiconductor element and electrodes electrically connected to the semiconductor element, the semiconductor element and the electrodes being sealed by a sealing agent having an insulating property, the electrodes being exposed around a mounting surface that is joined via a joining agent to an external mounting circuit board, wherein the electrodes are shaped so that the joining agent is visually identifiable from side surfaces surrounding the mounting surface when the mounting surface is joined via the joining agent to the mounting circuit board.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: September 4, 2007
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Koujiro Kameyama, Kiyoshi Mita
  • Patent number: 7213333
    Abstract: Provided are a method for manufacturing a mounting substrate and a method for manufacturing a circuit device, both of which include the step of electroplating a number of electrodes. The method for manufacturing a mounting substrate includes the steps of: forming a plurality of electrodes to a mounting substrate, the plurality of electrodes being electrically connected to each other by use of plating wires; energizing the electrodes via the plating wires to coat the electrodes with plated films 19 by electroplating; and electrically separating the individual electrodes from each other by cutting off the plating wires. Furthermore, the method for manufacturing a circuit device includes, in addition to the foregoing method for manufacturing a mounting substrate, the steps of: fixing a circuit element on the mounting substrate and electrically connecting the electrodes with the circuit element; and forming a sealing resin so as to cover the circuit element.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: May 8, 2007
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventor: Kiyoshi Mita
  • Publication number: 20070090521
    Abstract: It is an object of the present invention to provide a circuit device in which a plurality of circuit elements including a circuit element having a hollow inside are sealed with resin, and to provide a method of manufacturing the same. A circuit device (10) has a first circuit element (13A) having a hollow inside and a plurality of second circuit elements (13B) electrically connected to the first circuit element (13A). The first and second circuit elements (13A) and (13B) are sealed with sealing resin (15). The distances by which the first circuit element (13A) is separated from the second circuit elements (13B) are longer than those by which the second circuit elements (13B) are separated from each other.
    Type: Application
    Filed: September 1, 2004
    Publication date: April 26, 2007
    Applicants: SANYO ELECTRIC CO., LTD., KANTO SANYO SEMICONDUCTORS CO., LTD.
    Inventors: Hideo Imaizumi, Takuji Kato, Kenichi Nakajima, Masami Harigai, Masachika Kuwata, Isao Ochiai, Makoto Tsubonoya, Katsuhiko Shibusawa, Iwao Takase
  • Patent number: 7183589
    Abstract: To provide a semiconductor device 10, which is thin, compact, and excellent in mechanical strength and humidity resistance. Semiconductor device 10A has a configuration such that in semiconductor device 10A, wherein an optical semiconductor element 14, having a light receiving part or a light emitting part, is sealed in a sealing resin 13, a cover layer 12, covering the top surface of optical semiconductor element 14, is exposed from the top surface of sealing resin 13. Thus in comparison to a related-art example with which the entirety is sealed by a transparent resin, sealing resin 13 can be formed thinly and the thickness of the entire device can be made thin. Furthermore, semiconductor device 10 is arranged using a sealing resin having a filler mixed in. A semiconductor device that is excellent in mechanical strength and humidity resistance can thus be arranged.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: February 27, 2007
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Koujiro Kameyama, Kiyoshi Mita
  • Publication number: 20070035020
    Abstract: A semiconductor apparatus includes a semiconductor substrate, a through-electrode, a solder bump, and a circuit element. The semiconductor substrate has an electronic device formed on its front face. The through-electrode extends through the semiconductor substrate. The solder bump is disposed on the front side of the semiconductor substrate. The circuit element is disposed on the back side of the semiconductor substrate and is connected via the through-electrode to the electronic device.
    Type: Application
    Filed: December 16, 2005
    Publication date: February 15, 2007
    Applicants: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventor: Mitsuo Umemoto
  • Publication number: 20070034995
    Abstract: An optical semiconductor device of which the moisture resistance and the like are improved and the manufacturing method thereof are provided. An optical semiconductor device of the embodiment is configured to include an optical semiconductor element on a surface of which a circuit portion including a light-receiving or light-emitting element is formed; a terminal portion which is provided on a back of the optical semiconductor element and electrically connected with the circuit portion; a covering layer which covers the surface of the optical semiconductor element and is made of a transparent material; and sealing resin which covers side faces of the covering layer and of the optical semiconductor element. The circuit portion and the terminal portion may be connected by a rewiring pattern.
    Type: Application
    Filed: September 29, 2006
    Publication date: February 15, 2007
    Applicants: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Koujiro Kameyama, Kiyoshi Mita
  • Patent number: 7152316
    Abstract: To provide a hybrid integrated circuit device in which the rear surface of a circuit board is exposed to the outside and a method of manufacturing the same. Here, leads are fixed to the surface of the circuit board along one side thereof. A method of manufacturing a hybrid integrated circuit device includes the steps of forming an electric circuit which includes a conductive pattern formed on a surface of a circuit board and a circuit element electrically connected to the conductive pattern, fixing a lead to a pad formed of the conductive pattern, housing the circuit board in a cavity of molds, and fixedly supporting the lead by clamping the lead between the molds, and performing sealing by filling inside of the cavity with sealing resin with the rear surface of the circuit board made in contact with an inside bottom surface of the molds.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: December 26, 2006
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Haruhiko Mori, Masaru Kanakubo, Hideyuki Sakamoto
  • Patent number: 7105384
    Abstract: A circuit device manufacturing method is provided, wherein contaminants attached to the top surfaces of conductive patterns 21 are removed using plasma to thereby improve the adhesion of conductive patterns 21 to a sealing resin 28. By selective etching of a conductive foil 10, separation grooves 11 are formed, thereby forming conductive patterns 21. A semiconductor element 22A and other circuit elements are mounted onto desired locations of conductive patterns 21 and electrically connected with conductive patterns 21. By irradiating plasma onto conductive foil 10 from above, contaminants attached to the surfaces of separation grooves 11 are removed.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: September 12, 2006
    Assignees: Sanyo Electric Co., Ltd, Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Noriaki Sakamoto
  • Patent number: 7102211
    Abstract: The related arts have difficulty in efficiently dissipating the heat generated by a resin-molded semiconductor element, and thus have the problem of thermal stress causing damage to the semiconductor element. To solve the problem, a semiconductor device of the preferred embodiments includes common leads coupled to an island, and a part of the common leads projects out from a resin seal body. The projecting common leads have a coupling portion. When mounting the semiconductor device, the common leads are bridged with brazing material. Thus, the heat generated by an integrated circuit chip mounted on the island is dissipated through the common leads to the outside of the resin seal body. In the preferred embodiments of the invention, a further improvement in heat dissipation characteristics can be accomplished by increasing the surface areas of the common leads.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: September 5, 2006
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Isao Ochiai, Masato Take
  • Publication number: 20060176137
    Abstract: A semiconductor apparatus having a semiconductor chip, a first coil electrically connected to the semiconductor chip and a first electrode electrically connected to the first coil is comprised of a second electrode which can be electrically connected to the first electrode as well as which can be electrically connected to a second coil on the outside of the semiconductor apparatus, and is characterized by that inductance composed of the first coil and the second coil is obtained by electrically connecting the second electrode to the first electrode and the second coil.
    Type: Application
    Filed: January 24, 2006
    Publication date: August 10, 2006
    Applicants: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Akihiro Sato, Satoru Sekiguchi, Kiyokazu Kamado, Makoto Tsubonoya, Kiyoshi Mita, Yoichi Nabeta
  • Patent number: 7075188
    Abstract: In order to provide a circuit device 10 where a second circuit element 15B is exposed from a sealing resin 16, a circuit device 10A comprises: an island 12 to whose top a first circuit element 15A is fixedly fitted; a plurality of leads 11 which are extended around the island 12 and electrically connected to the first circuit element 15A; a sealing resin 16 which seals the first circuit element 15A, the island 12, and leads 11 and forms a cavity portion 18; and a second circuit element 15B stored in the cavity portion 18. Accordingly, since the second circuit element 15B can be externally provided, the degree of freedom for mounting can be improved.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: July 11, 2006
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Takuji Kato, Isao Ochiai, Katsuhiko Shibusawa
  • Publication number: 20060131724
    Abstract: A semiconductor apparatus comprises a substrate, a semiconductor chip fixedly secured on one side of the substrate, a spirally shaped coil formed on the other side of the substrate and electrically connected to the semiconductor chip, and a conductive pattern formed on a surface of the one side of the substrate facing to the semiconductor chip for stabilizing an inductance characteristic of the coil.
    Type: Application
    Filed: December 20, 2005
    Publication date: June 22, 2006
    Applicants: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Akihiro Sato, Satoru Sekiguchi, Kiyokazu Kamado, Kazunari Kurokawa, Makoto Tsubonoya, Kiyoshi Mita, Yoichi Nabeta, Tetsuro Sawai, Toshikazu Imaoka