Abstract: Aspects of the disclosure provide a method and an apparatus for clock and data recovery. The method and apparatus can increase jitter tolerance, and can provide recovered data with reduced jitter amplitude. The method for recovering data transmitted over a channel can include detecting a phase of a data transition within a full unit interval that includes an active zone and an inactive zone that are set based on a jitter characteristic for the channel, generating a phase directive when the phase of the data transition is located within the active zone, and adjusting a data sampling phase based on the phase directive, so that the data transmitted over the channel is sampled at a data transition edge free location.

Abstract: Aspects of the disclosure provide a method and an apparatus for clock and data recovery. The method and apparatus can increase jitter tolerance, and can provide recovered data with reduced jitter amplitude. The method for recovering data transmitted over a channel can include detecting a phase of a data transition within a full unit interval that includes an active zone and an inactive zone that are set based on a jitter characteristic for the channel, generating a phase directive when the phase of the data transition is located within the active zone, and adjusting a data sampling phase based on the phase directive, so that the data transmitted over the channel is sampled at a data transition edge free location.

Abstract: An equalizer may use a passive input stage to improve linearity and reduce power consumption. In addition, the equalizer may use two gain circuits, one in a high frequency amplification path and the other in an all-pass path. The relative proportion of all-pass to high frequency amplification may be adjusted using a single control signal. The equalizer may provide 20 dB of peaking at 5 GHz with good linearity, using CMOS technology.

Abstract: An adaptive equalizer may use dual loop adaptation to improve the performance of the equalizer. The first feedback loop may generate a boost control signal, based on the signal input to and output from a slicer. A second feedback loop may correct the swing amplitude of the slicer, so that the swing of the output matches the swing of the input.

Abstract: An equalizer may use reverse scaling of physical dimensions between a plurality of equalizer stages to improve overall bandwidth. The equalizer may provide 20 dB of peaking at 5 GHz with good linearity and little noise accumulation, using CMOS technology.

Abstract: An equalizer may use a passive input stage to improve linearity and reduce power consumption. In addition, the equalizer may use two gain circuits, one in a high frequency amplification path and the other in an all-pass path. The relative proportion of all-pass to high frequency amplification may be adjusted using a single control signal. The equalizer may provide 20 dB of peaking at 5 GHz with good linearity, using CMOS technology.